| Brad Bishop | bec4ebc | 2022-08-03 09:55:16 -0400 | [diff] [blame] | 1 | From 1a051bef6c63f6871edd8d87e969460f073820a7 Mon Sep 17 00:00:00 2001 |
| 2 | From: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com> |
| 3 | Date: Wed, 27 Apr 2022 18:15:47 +0100 |
| 4 | Subject: [PATCH 7/7] fix(plat/tc): disable smmu |
| 5 | |
| 6 | Reserve static shared-dma-pool below 4GB. This removes dependency on |
| 7 | SMMU driver. As there are stability issues in SMMU driver, it is |
| 8 | disabled. This change is temporary and will be reverted upon proper |
| 9 | fix and testing. |
| 10 | |
| 11 | Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com> |
| 12 | Change-Id: I6b1b4c2a0acdf62df8c26007c7ca596774e13710 |
| 13 | Upstream-Status: Pending [Not submitted to upstream yet] |
| 14 | --- |
| 15 | fdts/tc.dts | 16 +++------------- |
| 16 | 1 file changed, 3 insertions(+), 13 deletions(-) |
| 17 | |
| 18 | diff --git a/fdts/tc.dts b/fdts/tc.dts |
| 19 | index dc86958bf..fbae3e3e8 100644 |
| 20 | --- a/fdts/tc.dts |
| 21 | +++ b/fdts/tc.dts |
| 22 | @@ -209,12 +209,12 @@ |
| 23 | linux,cma { |
| 24 | compatible = "shared-dma-pool"; |
| 25 | reusable; |
| 26 | - size = <0x0 0x8000000>; |
| 27 | + reg = <0x0 0xf1000000 0x0 0x8000000>; |
| 28 | linux,cma-default; |
| 29 | }; |
| 30 | |
| 31 | - optee@0xf8e00000 { |
| 32 | - reg = <0x00000000 0xf8e00000 0 0x00200000>; |
| 33 | + optee@0xf0e00000 { |
| 34 | + reg = <0x0 0xf0e00000 0 0x00200000>; |
| 35 | no-map; |
| 36 | }; |
| 37 | }; |
| 38 | @@ -460,13 +460,6 @@ |
| 39 | >; |
| 40 | }; |
| 41 | |
| 42 | - smmu: smmu@2ce00000 { |
| 43 | - #iommu-cells = <1>; |
| 44 | - compatible = "arm,smmu-v3"; |
| 45 | - reg = <0x0 0x2ce00000 0x0 0x20000>; |
| 46 | - status = "okay"; |
| 47 | - }; |
| 48 | - |
| 49 | dp0: display@2cc00000 { |
| 50 | #address-cells = <1>; |
| 51 | #size-cells = <0>; |
| 52 | @@ -476,9 +469,6 @@ |
| 53 | interrupt-names = "DPU"; |
| 54 | clocks = <&scmi_clk 0>; |
| 55 | clock-names = "aclk"; |
| 56 | - iommus = <&smmu 0>, <&smmu 1>, <&smmu 2>, <&smmu 3>, |
| 57 | - <&smmu 4>, <&smmu 5>, <&smmu 6>, <&smmu 7>, |
| 58 | - <&smmu 8>, <&smmu 9>; |
| 59 | pl0: pipeline@0 { |
| 60 | reg = <0>; |
| 61 | clocks = <&scmi_clk 1>; |
| 62 | -- |
| 63 | 2.30.2 |
| 64 | |