Andrew Geissler | d159c7f | 2021-09-02 21:05:58 -0500 | [diff] [blame] | 1 | |
| 2 | # Right now this is focused on arm-specific tune features. |
| 3 | # We get away with this for now as one can only use x86-64 as the build host |
| 4 | # (not arm). |
| 5 | # Note that TUNE_FEATURES is _always_ refering to the target, so we really |
| 6 | # don't want to use this for the host/build. |
| 7 | def llvm_features_from_tune(d): |
| 8 | f = [] |
| 9 | feat = d.getVar('TUNE_FEATURES') |
| 10 | if not feat: |
| 11 | return [] |
| 12 | feat = frozenset(feat.split()) |
| 13 | |
| 14 | mach_overrides = d.getVar('MACHINEOVERRIDES') |
| 15 | mach_overrides = frozenset(mach_overrides.split(':')) |
| 16 | |
| 17 | if 'vfpv4' in feat: |
| 18 | f.append("+vfp4") |
| 19 | if 'vfpv3' in feat: |
| 20 | f.append("+vfp3") |
| 21 | if 'vfpv3d16' in feat: |
| 22 | f.append("+d16") |
| 23 | |
| 24 | if 'vfpv2' in feat or 'vfp' in feat: |
| 25 | f.append("+vfp2") |
| 26 | |
| 27 | if 'neon' in feat: |
| 28 | f.append("+neon") |
| 29 | |
| 30 | if 'mips32' in feat: |
| 31 | f.append("+mips32") |
| 32 | |
| 33 | if 'mips32r2' in feat: |
| 34 | f.append("+mips32r2") |
| 35 | |
| 36 | if target_is_armv7(d): |
| 37 | f.append('+v7') |
| 38 | |
| 39 | if ('armv6' in mach_overrides) or ('armv6' in feat): |
| 40 | f.append("+v6") |
| 41 | if 'armv5te' in feat: |
| 42 | f.append("+strict-align") |
| 43 | f.append("+v5te") |
| 44 | elif 'armv5' in feat: |
| 45 | f.append("+strict-align") |
| 46 | f.append("+v5") |
| 47 | |
| 48 | if ('armv4' in mach_overrides) or ('armv4' in feat): |
| 49 | f.append("+strict-align") |
| 50 | |
| 51 | if 'dsp' in feat: |
| 52 | f.append("+dsp") |
| 53 | |
| 54 | if 'thumb' in feat: |
| 55 | if d.getVar('ARM_THUMB_OPT') == "thumb": |
| 56 | if target_is_armv7(d): |
| 57 | f.append('+thumb2') |
| 58 | f.append("+thumb-mode") |
| 59 | |
| 60 | if 'cortexa5' in feat: |
| 61 | f.append("+a5") |
| 62 | if 'cortexa7' in feat: |
| 63 | f.append("+a7") |
| 64 | if 'cortexa9' in feat: |
| 65 | f.append("+a9") |
| 66 | if 'cortexa15' in feat: |
| 67 | f.append("+a15") |
| 68 | if 'cortexa17' in feat: |
| 69 | f.append("+a17") |
| 70 | if ('riscv64' in feat) or ('riscv32' in feat): |
| 71 | f.append("+a,+c,+d,+f,+m") |
| 72 | return f |
| 73 | llvm_features_from_tune[vardepvalue] = "${@llvm_features_from_tune(d)}" |
| 74 | |
| 75 | # TARGET_CC_ARCH changes from build/cross/target so it'll do the right thing |
| 76 | # this should go away when https://github.com/rust-lang/rust/pull/31709 is |
| 77 | # stable (1.9.0?) |
| 78 | def llvm_features_from_cc_arch(d): |
| 79 | f = [] |
| 80 | feat = d.getVar('TARGET_CC_ARCH') |
| 81 | if not feat: |
| 82 | return [] |
| 83 | feat = frozenset(feat.split()) |
| 84 | |
| 85 | if '-mmmx' in feat: |
| 86 | f.append("+mmx") |
| 87 | if '-msse' in feat: |
| 88 | f.append("+sse") |
| 89 | if '-msse2' in feat: |
| 90 | f.append("+sse2") |
| 91 | if '-msse3' in feat: |
| 92 | f.append("+sse3") |
| 93 | if '-mssse3' in feat: |
| 94 | f.append("+ssse3") |
| 95 | if '-msse4.1' in feat: |
| 96 | f.append("+sse4.1") |
| 97 | if '-msse4.2' in feat: |
| 98 | f.append("+sse4.2") |
| 99 | if '-msse4a' in feat: |
| 100 | f.append("+sse4a") |
| 101 | if '-mavx' in feat: |
| 102 | f.append("+avx") |
| 103 | if '-mavx2' in feat: |
| 104 | f.append("+avx2") |
| 105 | |
| 106 | return f |
| 107 | |
| 108 | def llvm_features_from_target_fpu(d): |
| 109 | # TARGET_FPU can be hard or soft. +soft-float tell llvm to use soft float |
| 110 | # ABI. There is no option for hard. |
| 111 | |
| 112 | fpu = d.getVar('TARGET_FPU', True) |
| 113 | return ["+soft-float"] if fpu == "soft" else [] |
| 114 | |
| 115 | def llvm_features(d): |
| 116 | return ','.join(llvm_features_from_tune(d) + |
| 117 | llvm_features_from_cc_arch(d) + |
| 118 | llvm_features_from_target_fpu(d)) |
| 119 | |
| 120 | |
| 121 | ## arm-unknown-linux-gnueabihf |
Andrew Geissler | eff2747 | 2021-10-29 15:35:00 -0500 | [diff] [blame] | 122 | DATA_LAYOUT[arm-eabi] = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" |
| 123 | LLVM_TARGET[arm-eabi] = "${RUST_TARGET_SYS}" |
| 124 | TARGET_ENDIAN[arm-eabi] = "little" |
| 125 | TARGET_POINTER_WIDTH[arm-eabi] = "32" |
| 126 | TARGET_C_INT_WIDTH[arm-eabi] = "32" |
| 127 | MAX_ATOMIC_WIDTH[arm-eabi] = "64" |
| 128 | FEATURES[arm-eabi] = "+v6,+vfp2" |
Andrew Geissler | d159c7f | 2021-09-02 21:05:58 -0500 | [diff] [blame] | 129 | |
| 130 | ## armv7-unknown-linux-gnueabihf |
Andrew Geissler | eff2747 | 2021-10-29 15:35:00 -0500 | [diff] [blame] | 131 | DATA_LAYOUT[armv7-eabi] = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" |
| 132 | LLVM_TARGET[armv7-eabi] = "${RUST_TARGET_SYS}" |
| 133 | TARGET_ENDIAN[armv7-eabi] = "little" |
| 134 | TARGET_POINTER_WIDTH[armv7-eabi] = "32" |
| 135 | TARGET_C_INT_WIDTH[armv7-eabi] = "32" |
| 136 | MAX_ATOMIC_WIDTH[armv7-eabi] = "64" |
| 137 | FEATURES[armv7-eabi] = "+v7,+vfp2,+thumb2" |
Andrew Geissler | d159c7f | 2021-09-02 21:05:58 -0500 | [diff] [blame] | 138 | |
| 139 | ## aarch64-unknown-linux-{gnu, musl} |
| 140 | DATA_LAYOUT[aarch64] = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128" |
| 141 | LLVM_TARGET[aarch64] = "${RUST_TARGET_SYS}" |
| 142 | TARGET_ENDIAN[aarch64] = "little" |
| 143 | TARGET_POINTER_WIDTH[aarch64] = "64" |
| 144 | TARGET_C_INT_WIDTH[aarch64] = "32" |
| 145 | MAX_ATOMIC_WIDTH[aarch64] = "128" |
| 146 | |
| 147 | ## x86_64-unknown-linux-{gnu, musl} |
| 148 | DATA_LAYOUT[x86_64] = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" |
| 149 | LLVM_TARGET[x86_64] = "${RUST_TARGET_SYS}" |
| 150 | TARGET_ENDIAN[x86_64] = "little" |
| 151 | TARGET_POINTER_WIDTH[x86_64] = "64" |
| 152 | TARGET_C_INT_WIDTH[x86_64] = "32" |
| 153 | MAX_ATOMIC_WIDTH[x86_64] = "64" |
| 154 | |
Andrew Geissler | eff2747 | 2021-10-29 15:35:00 -0500 | [diff] [blame] | 155 | ## x86_64-unknown-linux-gnux32 |
| 156 | DATA_LAYOUT[x86_64-x32] = "e-m:e-p:32:32-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" |
| 157 | LLVM_TARGET[x86_64-x32] = "${RUST_TARGET_SYS}" |
| 158 | TARGET_ENDIAN[x86_64-x32] = "little" |
| 159 | TARGET_POINTER_WIDTH[x86_64-x32] = "32" |
| 160 | TARGET_C_INT_WIDTH[x86_64-x32] = "32" |
| 161 | MAX_ATOMIC_WIDTH[x86_64-x32] = "64" |
| 162 | |
Andrew Geissler | d159c7f | 2021-09-02 21:05:58 -0500 | [diff] [blame] | 163 | ## i686-unknown-linux-{gnu, musl} |
| 164 | DATA_LAYOUT[i686] = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128" |
| 165 | LLVM_TARGET[i686] = "${RUST_TARGET_SYS}" |
| 166 | TARGET_ENDIAN[i686] = "little" |
| 167 | TARGET_POINTER_WIDTH[i686] = "32" |
| 168 | TARGET_C_INT_WIDTH[i686] = "32" |
| 169 | MAX_ATOMIC_WIDTH[i686] = "64" |
| 170 | |
| 171 | ## XXX: a bit of a hack so qemux86 builds, clone of i686-unknown-linux-{gnu, musl} above |
| 172 | DATA_LAYOUT[i586] = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128" |
| 173 | LLVM_TARGET[i586] = "${RUST_TARGET_SYS}" |
| 174 | TARGET_ENDIAN[i586] = "little" |
| 175 | TARGET_POINTER_WIDTH[i586] = "32" |
| 176 | TARGET_C_INT_WIDTH[i586] = "32" |
| 177 | MAX_ATOMIC_WIDTH[i586] = "64" |
| 178 | |
| 179 | ## mips-unknown-linux-{gnu, musl} |
| 180 | DATA_LAYOUT[mips] = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64" |
| 181 | LLVM_TARGET[mips] = "${RUST_TARGET_SYS}" |
| 182 | TARGET_ENDIAN[mips] = "big" |
| 183 | TARGET_POINTER_WIDTH[mips] = "32" |
| 184 | TARGET_C_INT_WIDTH[mips] = "32" |
| 185 | MAX_ATOMIC_WIDTH[mips] = "32" |
| 186 | |
| 187 | ## mipsel-unknown-linux-{gnu, musl} |
| 188 | DATA_LAYOUT[mipsel] = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64" |
| 189 | LLVM_TARGET[mipsel] = "${RUST_TARGET_SYS}" |
| 190 | TARGET_ENDIAN[mipsel] = "little" |
| 191 | TARGET_POINTER_WIDTH[mipsel] = "32" |
| 192 | TARGET_C_INT_WIDTH[mipsel] = "32" |
| 193 | MAX_ATOMIC_WIDTH[mipsel] = "32" |
| 194 | |
| 195 | ## mips64-unknown-linux-{gnu, musl} |
| 196 | DATA_LAYOUT[mips64] = "E-m:e-i8:8:32-i16:16:32-i64:64-n32:64-S128" |
| 197 | LLVM_TARGET[mips64] = "${RUST_TARGET_SYS}" |
| 198 | TARGET_ENDIAN[mips64] = "big" |
| 199 | TARGET_POINTER_WIDTH[mips64] = "64" |
| 200 | TARGET_C_INT_WIDTH[mips64] = "64" |
| 201 | MAX_ATOMIC_WIDTH[mips64] = "64" |
| 202 | |
| 203 | ## mips64el-unknown-linux-{gnu, musl} |
| 204 | DATA_LAYOUT[mips64el] = "e-m:e-i8:8:32-i16:16:32-i64:64-n32:64-S128" |
| 205 | LLVM_TARGET[mips64el] = "${RUST_TARGET_SYS}" |
| 206 | TARGET_ENDIAN[mips64el] = "little" |
| 207 | TARGET_POINTER_WIDTH[mips64el] = "64" |
| 208 | TARGET_C_INT_WIDTH[mips64el] = "64" |
| 209 | MAX_ATOMIC_WIDTH[mips64el] = "64" |
| 210 | |
| 211 | ## powerpc-unknown-linux-{gnu, musl} |
| 212 | DATA_LAYOUT[powerpc] = "E-m:e-p:32:32-i64:64-n32" |
| 213 | LLVM_TARGET[powerpc] = "${RUST_TARGET_SYS}" |
| 214 | TARGET_ENDIAN[powerpc] = "big" |
| 215 | TARGET_POINTER_WIDTH[powerpc] = "32" |
| 216 | TARGET_C_INT_WIDTH[powerpc] = "32" |
| 217 | MAX_ATOMIC_WIDTH[powerpc] = "32" |
| 218 | |
Andrew Geissler | eff2747 | 2021-10-29 15:35:00 -0500 | [diff] [blame] | 219 | ## powerpc64-unknown-linux-{gnu, musl} |
| 220 | DATA_LAYOUT[powerpc64] = "E-m:e-i64:64-n32:64-S128-v256:256:256-v512:512:512" |
| 221 | LLVM_TARGET[powerpc64] = "${RUST_TARGET_SYS}" |
| 222 | TARGET_ENDIAN[powerpc64] = "big" |
| 223 | TARGET_POINTER_WIDTH[powerpc64] = "64" |
| 224 | TARGET_C_INT_WIDTH[powerpc64] = "64" |
| 225 | MAX_ATOMIC_WIDTH[powerpc64] = "64" |
| 226 | |
Andrew Geissler | d159c7f | 2021-09-02 21:05:58 -0500 | [diff] [blame] | 227 | ## powerpc64le-unknown-linux-{gnu, musl} |
| 228 | DATA_LAYOUT[powerpc64le] = "e-m:e-i64:64-n32:64-v256:256:256-v512:512:512" |
| 229 | LLVM_TARGET[powerpc64le] = "${RUST_TARGET_SYS}" |
| 230 | TARGET_ENDIAN[powerpc64le] = "little" |
| 231 | TARGET_POINTER_WIDTH[powerpc64le] = "64" |
| 232 | TARGET_C_INT_WIDTH[powerpc64le] = "64" |
| 233 | MAX_ATOMIC_WIDTH[powerpc64le] = "64" |
| 234 | |
| 235 | ## riscv32-unknown-linux-{gnu, musl} |
| 236 | DATA_LAYOUT[riscv32] = "e-m:e-p:32:32-i64:64-n32-S128" |
| 237 | LLVM_TARGET[riscv32] = "${RUST_TARGET_SYS}" |
| 238 | TARGET_ENDIAN[riscv32] = "little" |
| 239 | TARGET_POINTER_WIDTH[riscv32] = "32" |
| 240 | TARGET_C_INT_WIDTH[riscv32] = "32" |
| 241 | MAX_ATOMIC_WIDTH[riscv32] = "32" |
| 242 | |
| 243 | ## riscv64-unknown-linux-{gnu, musl} |
| 244 | DATA_LAYOUT[riscv64] = "e-m:e-p:64:64-i64:64-i128:128-n64-S128" |
| 245 | LLVM_TARGET[riscv64] = "${RUST_TARGET_SYS}" |
| 246 | TARGET_ENDIAN[riscv64] = "little" |
| 247 | TARGET_POINTER_WIDTH[riscv64] = "64" |
| 248 | TARGET_C_INT_WIDTH[riscv64] = "64" |
| 249 | MAX_ATOMIC_WIDTH[riscv64] = "64" |
| 250 | |
| 251 | def sys_for(d, thing): |
| 252 | return d.getVar('{}_SYS'.format(thing)) |
| 253 | |
| 254 | def prefix_for(d, thing): |
| 255 | return d.getVar('{}_PREFIX'.format(thing)) |
| 256 | |
| 257 | # Convert a normal arch (HOST_ARCH, TARGET_ARCH, BUILD_ARCH, etc) to something |
| 258 | # rust's internals won't choke on. |
| 259 | def arch_to_rust_target_arch(arch): |
| 260 | if arch == "i586" or arch == "i686": |
| 261 | return "x86" |
| 262 | elif arch == "mipsel": |
| 263 | return "mips" |
| 264 | elif arch == "mip64sel": |
| 265 | return "mips64" |
| 266 | elif arch == "armv7": |
| 267 | return "arm" |
| 268 | elif arch == "powerpc64le": |
| 269 | return "powerpc64" |
| 270 | else: |
| 271 | return arch |
| 272 | |
| 273 | # generates our target CPU value |
| 274 | def llvm_cpu(d): |
| 275 | cpu = d.getVar('PACKAGE_ARCH') |
| 276 | target = d.getVar('TRANSLATED_TARGET_ARCH') |
| 277 | |
| 278 | trans = {} |
| 279 | trans['corei7-64'] = "corei7" |
| 280 | trans['core2-32'] = "core2" |
| 281 | trans['x86-64'] = "x86-64" |
| 282 | trans['i686'] = "i686" |
| 283 | trans['i586'] = "i586" |
| 284 | trans['powerpc'] = "powerpc" |
| 285 | trans['mips64'] = "mips64" |
| 286 | trans['mips64el'] = "mips64" |
| 287 | trans['riscv64'] = "generic-rv64" |
| 288 | trans['riscv32'] = "generic-rv32" |
| 289 | |
| 290 | if target in ["mips", "mipsel"]: |
| 291 | feat = frozenset(d.getVar('TUNE_FEATURES').split()) |
| 292 | if "mips32r2" in feat: |
| 293 | trans['mipsel'] = "mips32r2" |
| 294 | trans['mips'] = "mips32r2" |
| 295 | elif "mips32" in feat: |
| 296 | trans['mipsel'] = "mips32" |
| 297 | trans['mips'] = "mips32" |
| 298 | |
| 299 | try: |
| 300 | return trans[cpu] |
| 301 | except: |
| 302 | return trans.get(target, "generic") |
| 303 | |
| 304 | TARGET_LLVM_CPU="${@llvm_cpu(d)}" |
| 305 | TARGET_LLVM_FEATURES = "${@llvm_features(d)}" |
| 306 | |
| 307 | # class-native implies TARGET=HOST, and TUNE_FEATURES only describes the real |
| 308 | # (original) target. |
| 309 | TARGET_LLVM_FEATURES:class-native = "${@','.join(llvm_features_from_cc_arch(d))}" |
| 310 | |
Andrew Geissler | eff2747 | 2021-10-29 15:35:00 -0500 | [diff] [blame] | 311 | def rust_gen_target(d, thing, wd, features, cpu, arch, abi=""): |
Andrew Geissler | d159c7f | 2021-09-02 21:05:58 -0500 | [diff] [blame] | 312 | import json |
| 313 | sys = sys_for(d, thing) |
| 314 | prefix = prefix_for(d, thing) |
| 315 | |
Andrew Jeffery | ecdf5f1 | 2022-03-01 01:09:46 +1030 | [diff] [blame^] | 316 | rust_arch = oe.rust.arch_to_rust_arch(arch) |
| 317 | |
Andrew Geissler | eff2747 | 2021-10-29 15:35:00 -0500 | [diff] [blame] | 318 | if abi: |
Andrew Jeffery | ecdf5f1 | 2022-03-01 01:09:46 +1030 | [diff] [blame^] | 319 | arch_abi = "{}-{}".format(rust_arch, abi) |
Andrew Geissler | eff2747 | 2021-10-29 15:35:00 -0500 | [diff] [blame] | 320 | else: |
Andrew Jeffery | ecdf5f1 | 2022-03-01 01:09:46 +1030 | [diff] [blame^] | 321 | arch_abi = rust_arch |
Andrew Geissler | eff2747 | 2021-10-29 15:35:00 -0500 | [diff] [blame] | 322 | |
| 323 | features = features or d.getVarFlag('FEATURES', arch_abi) or "" |
Andrew Geissler | d159c7f | 2021-09-02 21:05:58 -0500 | [diff] [blame] | 324 | features = features.strip() |
| 325 | |
| 326 | # build tspec |
| 327 | tspec = {} |
Andrew Geissler | eff2747 | 2021-10-29 15:35:00 -0500 | [diff] [blame] | 328 | tspec['llvm-target'] = d.getVarFlag('LLVM_TARGET', arch_abi) |
| 329 | tspec['data-layout'] = d.getVarFlag('DATA_LAYOUT', arch_abi) |
| 330 | tspec['max-atomic-width'] = int(d.getVarFlag('MAX_ATOMIC_WIDTH', arch_abi)) |
| 331 | tspec['target-pointer-width'] = d.getVarFlag('TARGET_POINTER_WIDTH', arch_abi) |
| 332 | tspec['target-c-int-width'] = d.getVarFlag('TARGET_C_INT_WIDTH', arch_abi) |
| 333 | tspec['target-endian'] = d.getVarFlag('TARGET_ENDIAN', arch_abi) |
Andrew Jeffery | ecdf5f1 | 2022-03-01 01:09:46 +1030 | [diff] [blame^] | 334 | tspec['arch'] = arch_to_rust_target_arch(rust_arch) |
Andrew Geissler | d159c7f | 2021-09-02 21:05:58 -0500 | [diff] [blame] | 335 | tspec['os'] = "linux" |
| 336 | if "musl" in tspec['llvm-target']: |
| 337 | tspec['env'] = "musl" |
| 338 | else: |
| 339 | tspec['env'] = "gnu" |
| 340 | if "riscv64" in tspec['llvm-target']: |
| 341 | tspec['llvm-abiname'] = "lp64d" |
| 342 | if "riscv32" in tspec['llvm-target']: |
| 343 | tspec['llvm-abiname'] = "ilp32d" |
| 344 | tspec['vendor'] = "unknown" |
| 345 | tspec['target-family'] = "unix" |
| 346 | tspec['linker'] = "{}{}gcc".format(d.getVar('CCACHE'), prefix) |
Andrew Geissler | d159c7f | 2021-09-02 21:05:58 -0500 | [diff] [blame] | 347 | tspec['cpu'] = cpu |
| 348 | if features != "": |
| 349 | tspec['features'] = features |
| 350 | tspec['dynamic-linking'] = True |
| 351 | tspec['executables'] = True |
| 352 | tspec['linker-is-gnu'] = True |
| 353 | tspec['linker-flavor'] = "gcc" |
| 354 | tspec['has-rpath'] = True |
| 355 | tspec['has-elf-tls'] = True |
| 356 | tspec['position-independent-executables'] = True |
| 357 | tspec['panic-strategy'] = d.getVar("RUST_PANIC_STRATEGY") |
| 358 | |
| 359 | # write out the target spec json file |
| 360 | with open(wd + sys + '.json', 'w') as f: |
| 361 | json.dump(tspec, f, indent=4) |
| 362 | |
| 363 | python do_rust_gen_targets () { |
| 364 | wd = d.getVar('WORKDIR') + '/targets/' |
| 365 | build_arch = d.getVar('BUILD_ARCH') |
| 366 | rust_gen_target(d, 'BUILD', wd, "", "generic", build_arch) |
| 367 | } |
| 368 | |
| 369 | addtask rust_gen_targets after do_patch before do_compile |
| 370 | do_rust_gen_targets[dirs] += "${WORKDIR}/targets" |
| 371 | |