meta-ethanolx/recipes-kernel/linux/linux-aspeed/0001-linux-aspeed-dts-Initial-device-tree-for-AMD-Ethanol.patch

From 3edccfb5c904041b784618ae5451ffea03d15acb Mon Sep 17 00:00:00 2001
From: Supreeth Venkatesh <supreeth.venkatesh@amd.com>
Date: Wed, 27 May 2020 14:45:32 -0500
Subject: [PATCH] linux-aspeed/dts: Initial device tree for AMD EthanolX

This patch provides initial device tree for AMD EthanolX platform.
It describes I2c devices, Fans, Kcs devices, Uarts, Mac, LEDs, etc.

Signed-off-by: Supreeth Venkatesh <supreeth.venkatesh@amd.com>
---
 arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts | 305 ++++++++++++++++++
 1 file changed, 305 insertions(+)
 create mode 100644 arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts

diff --git a/arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts b/arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts
new file mode 100644
index 000000000000..d97bf9b9de96
--- /dev/null
+++ b/arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts
@@ -0,0 +1,305 @@
+// SPDX-License-Identifier:	Apache v2
+// Copyright (c) 2020 AMD Inc.
+// Author: Supreeth Venkatesh <supreeth.venkatesh@amd.com>
+/dts-v1/;
+
+#include "aspeed-g5.dtsi"
+#include <dt-bindings/gpio/aspeed-gpio.h>
+
+/ {
+	model = "AMD EthanolX BMC";
+	compatible = "amd,ethanolx-bmc", "aspeed,ast2500";
+
+	memory@80000000 {
+		reg = <0x80000000 0x20000000>;
+	};
+	aliases {
+		serial0 = &uart1;
+		serial4 = &uart5;
+	};
+	chosen {
+		stdout-path = &uart5;
+		bootargs = "console=ttyS4,115200 earlyprintk";
+	};
+	leds {
+	compatible = "gpio-leds";
+
+		fault {
+			gpios = <&gpio ASPEED_GPIO(A, 2) GPIO_ACTIVE_LOW>;
+		};
+
+		identify {
+			gpios = <&gpio ASPEED_GPIO(A, 3) GPIO_ACTIVE_LOW>;
+		};
+	};
+	iio-hwmon {
+		compatible = "iio-hwmon";
+		io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, <&adc 4>;
+	};
+};
+
+&fmc {
+	status = "okay";
+	flash@0 {
+		status = "okay";
+		m25p,fast-read;
+		#include "openbmc-flash-layout.dtsi"
+	};
+};
+
+
+&mac0 {
+	status = "okay";
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_rmii1_default>;
+	clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>,
+			 <&syscon ASPEED_CLK_MAC1RCLK>;
+	clock-names = "MACCLK", "RCLK";
+};
+
+&uart1 {
+	//Host Console
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_txd1_default
+				 &pinctrl_rxd1_default>;
+};
+
+&uart5 {
+	//BMC Console
+	status = "okay";
+};
+
+&adc {
+	status = "okay";
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_adc0_default
+			&pinctrl_adc1_default
+			&pinctrl_adc2_default
+			&pinctrl_adc3_default
+			&pinctrl_adc4_default>;
+};
+
+&i2c {
+	//APML for P0
+	i2c1: i2c-bus@80 {
+		reg = <0x80 0x40>;
+		status = "okay";
+	};
+
+	//APML for P1
+	i2c2: i2c-bus@c0 {
+		reg = <0xc0 0x40>;
+		status = "okay";
+	};
+
+	//FPGA Side band
+	i2c3: i2c-bus@100 {
+		reg = <0x100 0x40>;
+		status = "okay";
+	};
+
+	//BMC serial EEPROM
+	i2c4: i2c-bus@140 {
+		reg = <0x140 0x40>;
+		status = "okay";
+	};
+
+	//P0 Voltage Regulators
+	i2c5: i2c-bus@180 {
+		reg = <0x180 0x40>;
+		status = "okay";
+
+		isl69147@61 {
+			compatible = "renesas,isl69147";
+			reg = <0x61>;
+		};
+
+		isl69144@63 {
+			compatible = "renesas,isl69144";
+			reg = <0x63>;
+		};
+
+		isl68127@64 {
+			compatible = "renesas,isl68127";
+			reg = <0x64>;
+		};
+
+		isl68127@65 {
+			compatible = "renesas,isl68127";
+			reg = <0x65>;
+		};
+	};
+
+	//P1 Voltage Regulators
+	i2c6: i2c-bus@1c0 {
+		reg = <0x1c0 0x40>;
+		status = "okay";
+
+		isl69147@61 {
+			compatible = "renesas,isl69147";
+			reg = <0x61>;
+		};
+
+		isl69144@63 {
+			compatible = "renesas,isl69144";
+			reg = <0x63>;
+		};
+
+			isl68127@64 {
+			compatible = "renesas,isl68127";
+			reg = <0x64>;
+		};
+
+			isl68127@65 {
+			compatible = "renesas,isl68127";
+			reg = <0x65>;
+		};
+	};
+
+	//Backplane and NVMe
+	i2c7: i2c-bus@300 {
+		reg = <0x300 0x40>;
+		status = "okay";
+
+		mg9098@60 {
+			compatible = "ami,mg9098";
+			reg = <0x60>;
+		};
+
+		pca9545apw@70 {
+			compatible = "ti,pca9545apw";
+			reg = <0x70>;
+			//Todo: Map P1_NVME0_SMBUS...P1_NVME3_SMBUS
+		};
+	};
+
+	// Thermal Sensors
+	i2c8: i2c-bus@340 {
+		reg =	<0x340 0x40>;
+		status = "okay";
+
+		lm75a@48 {
+			compatible = "ti,lm75a";
+			reg = <0x48>;
+		};
+
+		lm75a@49 {
+			compatible = "ti,lm75a";
+			reg = <0x49>;
+		};
+
+		lm75a@4a {
+			compatible = "ti,lm75a";
+			reg = <0x4a>;
+		};
+
+		lm75a@4b {
+			compatible = "ti,lm75a";
+			reg = <0x4b>;
+		};
+
+		lm75a@4c {
+			compatible = "ti,lm75a";
+			reg = <0x4c>;
+		};
+
+		lm75a@4d {
+			compatible = "ti,lm75a";
+			reg = <0x4d>;
+		};
+
+		lm75a@4e {
+			compatible = "ti,lm75a";
+			reg = <0x4e>;
+		};
+
+		lm75a@4f {
+			compatible = "ti,lm75a";
+			reg = <0x4f>;
+		};
+	};
+};
+
+&kcs1 {
+	status = "okay";
+	kcs_addr = <0x60>;
+};
+
+&kcs2 {
+	status = "okay";
+	kcs_addr = <0x62>;
+};
+
+&kcs4 {
+	status = "okay";
+	kcs_addr = <0x97DE>;
+};
+
+&lpc_snoop {
+	status = "okay";
+	snoop-ports = <0x80>;
+};
+
+&lpc_ctrl {
+	//Enable lpc clock
+	status = "okay";
+};
+
+&pwm_tacho {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pwm0_default
+	&pinctrl_pwm1_default
+	&pinctrl_pwm2_default
+	&pinctrl_pwm3_default
+	&pinctrl_pwm4_default
+	&pinctrl_pwm5_default
+	&pinctrl_pwm6_default
+	&pinctrl_pwm7_default>;
+
+	fan@0 {
+		reg = <0x00>;
+		aspeed,fan-tach-ch = /bits/ 8 <0x00>;
+	};
+
+	fan@1 {
+		reg = <0x01>;
+		aspeed,fan-tach-ch = /bits/ 8 <0x01>;
+	};
+
+	fan@2 {
+		reg = <0x02>;
+		aspeed,fan-tach-ch = /bits/ 8 <0x02>;
+	};
+
+	fan@3 {
+		reg = <0x03>;
+		aspeed,fan-tach-ch = /bits/ 8 <0x03>;
+	};
+
+	fan@4 {
+		reg = <0x04>;
+		aspeed,fan-tach-ch = /bits/ 8 <0x04>;
+	};
+
+	fan@5 {
+		reg = <0x05>;
+		aspeed,fan-tach-ch = /bits/ 8 <0x05>;
+	};
+
+	fan@6 {
+		reg = <0x06>;
+		aspeed,fan-tach-ch = /bits/ 8 <0x06>;
+	};
+
+	fan@7 {
+		reg = <0x07>;
+		aspeed,fan-tach-ch = /bits/ 8 <0x07>;
+	};
+};
+
+
+
--
2.17.1