| Add support for RISC-V |
| |
| Upstream-Status: Pending |
| Signed-off-by: Khem Raj <raj.khem@gmail.com> |
| --- a/webrtc/base/basictypes.h |
| +++ b/webrtc/base/basictypes.h |
| @@ -29,6 +29,10 @@ |
| #define CPU_ARM 1 |
| #endif |
| |
| +#if defined(__riscv) || defined(_M_RISCV) |
| +#define CPU_RISCV 1 |
| +#endif |
| + |
| #if defined(CPU_X86) && defined(CPU_ARM) |
| #error CPU_X86 and CPU_ARM both defined. |
| #endif |
| --- a/webrtc/typedefs.h |
| +++ b/webrtc/typedefs.h |
| @@ -56,6 +56,13 @@ |
| #elif defined(__powerpc__) |
| #define WEBRTC_ARCH_32_BITS |
| #define WEBRTC_ARCH_BIG_ENDIAN |
| +#elif defined(__riscv) |
| +#if __riscv_xlen == 64 |
| +# define WEBRTC_ARCH_64_BITS |
| +#else |
| +# define WEBRTC_ARCH_32_BITS |
| +#endif |
| +#define WEBRTC_ARCH_LITTLE_ENDIAN |
| #elif defined(__pnacl__) |
| #define WEBRTC_ARCH_32_BITS |
| #define WEBRTC_ARCH_LITTLE_ENDIAN |