blob: 576b9860a88b170bd18ceaaf67f1b213cd1e16ea [file] [log] [blame]
Brad Bishop19323692019-04-05 15:28:33 -04001Add support for RISC-V
2
3Upstream-Status: Pending
4Signed-off-by: Khem Raj <raj.khem@gmail.com>
5--- a/webrtc/base/basictypes.h
6+++ b/webrtc/base/basictypes.h
7@@ -29,6 +29,10 @@
8 #define CPU_ARM 1
9 #endif
10
11+#if defined(__riscv) || defined(_M_RISCV)
12+#define CPU_RISCV 1
13+#endif
14+
15 #if defined(CPU_X86) && defined(CPU_ARM)
16 #error CPU_X86 and CPU_ARM both defined.
17 #endif
18--- a/webrtc/typedefs.h
19+++ b/webrtc/typedefs.h
20@@ -56,6 +56,13 @@
21 #elif defined(__powerpc__)
22 #define WEBRTC_ARCH_32_BITS
23 #define WEBRTC_ARCH_BIG_ENDIAN
24+#elif defined(__riscv)
25+#if __riscv_xlen == 64
26+# define WEBRTC_ARCH_64_BITS
27+#else
28+# define WEBRTC_ARCH_32_BITS
29+#endif
30+#define WEBRTC_ARCH_LITTLE_ENDIAN
31 #elif defined(__pnacl__)
32 #define WEBRTC_ARCH_32_BITS
33 #define WEBRTC_ARCH_LITTLE_ENDIAN