meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0012-Patch-microblaze-Added-ashrsi3_with_size_opt.patch

From 64f1a238641616c9cca5823d7ca99e76a7c2a490 Mon Sep 17 00:00:00 2001
From: Mahesh Bodapati <mbodapat@xilinx.com>
Date: Thu, 12 Jan 2017 16:52:56 +0530
Subject: [PATCH 12/54] [Patch, microblaze]: Added ashrsi3_with_size_opt Added
 ashrsi3_with_size_opt pattern to optimize the sra instructions when the -Os
 optimization is used. lshrsi3_with_size_opt is being removed as it has
 conflicts with unsigned int variables

Signed-off-by:Nagaraju Mekala <nmekala@xilix.com>
---
 gcc/config/microblaze/microblaze.md | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
index 93f5fa2..fe90a14 100644
--- a/gcc/config/microblaze/microblaze.md
+++ b/gcc/config/microblaze/microblaze.md
@@ -1506,6 +1506,27 @@
   (set_attr "length"	"4,4")]
 )
 
+(define_insn "*ashrsi3_with_size_opt"
+  [(set (match_operand:SI 0 "register_operand" "=&d")
+       (ashiftrt:SI (match_operand:SI 1 "register_operand"  "d")
+                   (match_operand:SI 2 "immediate_operand" "I")))]
+  "(INTVAL (operands[2]) > 5 && optimize_size)"
+  {
+    operands[3] = gen_rtx_REG (SImode, MB_ABI_ASM_TEMP_REGNUM);
+
+    output_asm_insn ("ori\t%3,r0,%2", operands);
+    if (REGNO (operands[0]) != REGNO (operands[1]))
+        output_asm_insn ("addk\t%0,%1,r0", operands);
+
+    output_asm_insn ("addik\t%3,%3,-1", operands);
+    output_asm_insn ("bneid\t%3,.-4", operands);
+    return "sra\t%0,%0";
+  }
+  [(set_attr "type"    "arith")
+  (set_attr "mode"    "SI")
+  (set_attr "length"  "20")]
+)
+
 (define_insn "*ashrsi_inline"
   [(set (match_operand:SI 0 "register_operand" "=&d")
        (ashiftrt:SI (match_operand:SI 1 "register_operand"  "d")
-- 
2.7.4