Patrick Williams | d8c66bc | 2016-06-20 12:57:21 -0500 | [diff] [blame] | 1 | From 9f967c555b3fda64af4549ae252a0fba00120529 Mon Sep 17 00:00:00 2001 |
| 2 | From: Khem Raj <raj.khem@gmail.com> |
| 3 | Date: Sun, 14 Feb 2016 17:06:19 +0000 |
| 4 | Subject: [PATCH 12/14] Add support for Netlogic XLP |
| 5 | |
| 6 | Patch From: Nebu Philips <nphilips@netlogicmicro.com> |
| 7 | |
| 8 | Using the mipsisa64r2nlm target, add support for XLP from |
| 9 | Netlogic. Also, update vendor name to NLM wherever applicable. |
| 10 | |
| 11 | Use 0x00000080 for INSN_XLP, the value 0x00000040 has already been |
| 12 | assigned to INSN_OCTEON3 |
| 13 | |
| 14 | Signed-off-by: Khem Raj <raj.khem@gmail.com> |
| 15 | Signed-off-by: Baoshan Pang <baoshan.pang@windriver.com> |
| 16 | Signed-off-by: Mark Hatle <mark.hatle@windriver.com> |
| 17 | --- |
| 18 | Upstream-Status: Pending |
| 19 | |
| 20 | bfd/aoutx.h | 1 + |
| 21 | bfd/archures.c | 1 + |
| 22 | bfd/bfd-in2.h | 1 + |
| 23 | bfd/config.bfd | 5 +++++ |
| 24 | bfd/cpu-mips.c | 6 ++++-- |
| 25 | bfd/elfxx-mips.c | 8 ++++++++ |
| 26 | binutils/readelf.c | 1 + |
| 27 | gas/config/tc-mips.c | 4 +++- |
| 28 | gas/configure | 3 +++ |
| 29 | gas/configure.tgt | 2 +- |
| 30 | include/elf/mips.h | 1 + |
| 31 | include/opcode/mips.h | 10 ++++++++-- |
| 32 | ld/configure.tgt | 2 ++ |
| 33 | opcodes/mips-dis.c | 12 +++++------- |
| 34 | opcodes/mips-opc.c | 33 +++++++++++++++++++++------------ |
| 35 | 15 files changed, 65 insertions(+), 25 deletions(-) |
| 36 | |
| 37 | diff --git a/bfd/aoutx.h b/bfd/aoutx.h |
| 38 | index f78b910..d0d8dd3 100644 |
| 39 | --- a/bfd/aoutx.h |
| 40 | +++ b/bfd/aoutx.h |
| 41 | @@ -802,6 +802,7 @@ NAME (aout, machine_type) (enum bfd_architecture arch, |
| 42 | case bfd_mach_mipsisa64r6: |
| 43 | case bfd_mach_mips_sb1: |
| 44 | case bfd_mach_mips_xlr: |
| 45 | + case bfd_mach_mips_xlp: |
| 46 | /* FIXME: These should be MIPS3, MIPS4, MIPS16, MIPS32, etc. */ |
| 47 | arch_flags = M_MIPS2; |
| 48 | break; |
| 49 | diff --git a/bfd/archures.c b/bfd/archures.c |
| 50 | index 51068b9..727741f 100644 |
| 51 | --- a/bfd/archures.c |
| 52 | +++ b/bfd/archures.c |
| 53 | @@ -181,6 +181,7 @@ DESCRIPTION |
| 54 | .#define bfd_mach_mips_octeon2 6502 |
| 55 | .#define bfd_mach_mips_octeon3 6503 |
| 56 | .#define bfd_mach_mips_xlr 887682 {* decimal 'XLR' *} |
| 57 | +.#define bfd_mach_mips_xlp 887680 {* decimal 'XLP' *} |
| 58 | .#define bfd_mach_mipsisa32 32 |
| 59 | .#define bfd_mach_mipsisa32r2 33 |
| 60 | .#define bfd_mach_mipsisa32r3 34 |
| 61 | diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h |
| 62 | index 779ffbf..bf5a565 100644 |
| 63 | --- a/bfd/bfd-in2.h |
| 64 | +++ b/bfd/bfd-in2.h |
| 65 | @@ -1993,6 +1993,7 @@ enum bfd_architecture |
| 66 | #define bfd_mach_mips_octeon2 6502 |
| 67 | #define bfd_mach_mips_octeon3 6503 |
| 68 | #define bfd_mach_mips_xlr 887682 /* decimal 'XLR' */ |
| 69 | +#define bfd_mach_mips_xlp 887680 /* decimal 'XLP' */ |
| 70 | #define bfd_mach_mipsisa32 32 |
| 71 | #define bfd_mach_mipsisa32r2 33 |
| 72 | #define bfd_mach_mipsisa32r3 34 |
| 73 | diff --git a/bfd/config.bfd b/bfd/config.bfd |
| 74 | index 5c27b49..d553039 100644 |
| 75 | --- a/bfd/config.bfd |
| 76 | +++ b/bfd/config.bfd |
| 77 | @@ -1066,6 +1066,11 @@ case "${targ}" in |
| 78 | targ_defvec=mips_elf32_le_vec |
| 79 | targ_selvecs="mips_elf32_be_vec mips_elf64_be_vec mips_elf64_le_vec" |
| 80 | ;; |
| 81 | + mipsisa64*-*-elf*) |
| 82 | + targ_defvec=mips_elf32_trad_be_vec |
| 83 | + targ_selvecs="mips_elf32_trad_le_vec mips_elf64_trad_be_vec mips_elf64_trad_le_vec" |
| 84 | + want64=true |
| 85 | + ;; |
| 86 | mips*-*-elf* | mips*-*-rtems* | mips*-*-vxworks | mips*-*-windiss) |
| 87 | targ_defvec=mips_elf32_be_vec |
| 88 | targ_selvecs="mips_elf32_le_vec mips_elf64_be_vec mips_elf64_le_vec" |
| 89 | diff --git a/bfd/cpu-mips.c b/bfd/cpu-mips.c |
| 90 | index 8a9475d..de7e5a3 100644 |
| 91 | --- a/bfd/cpu-mips.c |
| 92 | +++ b/bfd/cpu-mips.c |
| 93 | @@ -104,7 +104,8 @@ enum |
| 94 | I_mipsocteon2, |
| 95 | I_mipsocteon3, |
| 96 | I_xlr, |
| 97 | - I_micromips |
| 98 | + I_micromips, |
| 99 | + I_xlp |
| 100 | }; |
| 101 | |
| 102 | #define NN(index) (&arch_info_struct[(index) + 1]) |
| 103 | @@ -155,7 +156,8 @@ static const bfd_arch_info_type arch_info_struct[] = |
| 104 | N (64, 64, bfd_mach_mips_octeon2,"mips:octeon2", FALSE, NN(I_mipsocteon2)), |
| 105 | N (64, 64, bfd_mach_mips_octeon3, "mips:octeon3", FALSE, NN(I_mipsocteon3)), |
| 106 | N (64, 64, bfd_mach_mips_xlr, "mips:xlr", FALSE, NN(I_xlr)), |
| 107 | - N (64, 64, bfd_mach_mips_micromips,"mips:micromips",FALSE,0) |
| 108 | + N (64, 64, bfd_mach_mips_micromips,"mips:micromips",FALSE,NN(I_micromips)), |
| 109 | + N (64, 64, bfd_mach_mips_xlp, "mips:xlp", FALSE, 0) |
| 110 | }; |
| 111 | |
| 112 | /* The default architecture is mips:3000, but with a machine number of |
| 113 | diff --git a/bfd/elfxx-mips.c b/bfd/elfxx-mips.c |
| 114 | index 1f2f4a3..700afd3 100644 |
| 115 | --- a/bfd/elfxx-mips.c |
| 116 | +++ b/bfd/elfxx-mips.c |
| 117 | @@ -6605,6 +6605,9 @@ _bfd_elf_mips_mach (flagword flags) |
| 118 | case E_MIPS_MACH_XLR: |
| 119 | return bfd_mach_mips_xlr; |
| 120 | |
| 121 | + case E_MIPS_MACH_XLP: |
| 122 | + return bfd_mach_mips_xlp; |
| 123 | + |
| 124 | default: |
| 125 | switch (flags & EF_MIPS_ARCH) |
| 126 | { |
| 127 | @@ -11901,6 +11904,10 @@ mips_set_isa_flags (bfd *abfd) |
| 128 | val = E_MIPS_ARCH_64R2 | E_MIPS_MACH_OCTEON2; |
| 129 | break; |
| 130 | |
| 131 | + case bfd_mach_mips_xlp: |
| 132 | + val = E_MIPS_ARCH_64R2 | E_MIPS_MACH_XLP; |
| 133 | + break; |
| 134 | + |
| 135 | case bfd_mach_mipsisa32: |
| 136 | val = E_MIPS_ARCH_32; |
| 137 | break; |
| 138 | @@ -13931,6 +13938,7 @@ static const struct mips_mach_extension mips_mach_extensions[] = |
| 139 | { bfd_mach_mips_octeonp, bfd_mach_mips_octeon }, |
| 140 | { bfd_mach_mips_octeon, bfd_mach_mipsisa64r2 }, |
| 141 | { bfd_mach_mips_loongson_3a, bfd_mach_mipsisa64r2 }, |
| 142 | + { bfd_mach_mips_xlp, bfd_mach_mipsisa64r2 }, |
| 143 | |
| 144 | /* MIPS64 extensions. */ |
| 145 | { bfd_mach_mipsisa64r2, bfd_mach_mipsisa64 }, |
| 146 | diff --git a/binutils/readelf.c b/binutils/readelf.c |
| 147 | index d5dd46f..66810cc 100644 |
| 148 | --- a/binutils/readelf.c |
| 149 | +++ b/binutils/readelf.c |
| 150 | @@ -3140,6 +3140,7 @@ get_machine_flags (unsigned e_flags, unsigned e_machine) |
| 151 | case E_MIPS_MACH_OCTEON2: strcat (buf, ", octeon2"); break; |
| 152 | case E_MIPS_MACH_OCTEON3: strcat (buf, ", octeon3"); break; |
| 153 | case E_MIPS_MACH_XLR: strcat (buf, ", xlr"); break; |
| 154 | + case E_MIPS_MACH_XLP: strcat (buf, ", xlp"); break; |
| 155 | case 0: |
| 156 | /* We simply ignore the field in this case to avoid confusion: |
| 157 | MIPS ELF does not specify EF_MIPS_MACH, it is a GNU |
| 158 | diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c |
| 159 | index a2d45a4..75902c0 100644 |
| 160 | --- a/gas/config/tc-mips.c |
| 161 | +++ b/gas/config/tc-mips.c |
| 162 | @@ -552,6 +552,7 @@ static int mips_32bitmode = 0; |
| 163 | || mips_opts.arch == CPU_RM7000 \ |
| 164 | || mips_opts.arch == CPU_VR5500 \ |
| 165 | || mips_opts.micromips \ |
| 166 | + || mips_opts.arch == CPU_XLP \ |
| 167 | ) |
| 168 | |
| 169 | /* Whether the processor uses hardware interlocks to protect reads |
| 170 | @@ -581,6 +582,7 @@ static int mips_32bitmode = 0; |
| 171 | && mips_opts.isa != ISA_MIPS3) \ |
| 172 | || mips_opts.arch == CPU_R4300 \ |
| 173 | || mips_opts.micromips \ |
| 174 | + || mips_opts.arch == CPU_XLP \ |
| 175 | ) |
| 176 | |
| 177 | /* Whether the processor uses hardware interlocks to protect reads |
| 178 | @@ -18702,7 +18704,7 @@ static const struct mips_cpu_info mips_cpu_info_table[] = |
| 179 | /* Broadcom XLP. |
| 180 | XLP is mostly like XLR, with the prominent exception that it is |
| 181 | MIPS64R2 rather than MIPS64. */ |
| 182 | - { "xlp", 0, 0, ISA_MIPS64R2, CPU_XLR }, |
| 183 | + { "xlp", 0, 0, ISA_MIPS64R2, CPU_XLP }, |
| 184 | |
| 185 | /* i6400. */ |
| 186 | { "i6400", 0, ASE_MSA, ISA_MIPS64R6, CPU_MIPS64R6}, |
| 187 | diff --git a/gas/configure b/gas/configure |
| 188 | index 89f18b3..86b19ae 100755 |
| 189 | --- a/gas/configure |
| 190 | +++ b/gas/configure |
| 191 | @@ -12851,6 +12851,9 @@ _ACEOF |
| 192 | mipsisa64r6 | mipsisa64r6el) |
| 193 | mips_cpu=mips64r6 |
| 194 | ;; |
| 195 | + mipsisa64r2nlm | mipsisa64r2nlmel) |
| 196 | + mips_cpu=xlp |
| 197 | + ;; |
| 198 | mipstx39 | mipstx39el) |
| 199 | mips_cpu=r3900 |
| 200 | ;; |
| 201 | diff --git a/gas/configure.tgt b/gas/configure.tgt |
| 202 | index 086e0d2..2b71270 100644 |
| 203 | --- a/gas/configure.tgt |
| 204 | +++ b/gas/configure.tgt |
| 205 | @@ -339,7 +339,7 @@ case ${generic_target} in |
| 206 | mips-*-sysv4*MP* | mips-*-gnu*) fmt=elf em=tmips ;; |
| 207 | mips*-sde-elf* | mips*-mti-elf* | mips*-img-elf*) |
| 208 | fmt=elf em=tmips ;; |
| 209 | - mips-*-elf* | mips-*-rtems*) fmt=elf ;; |
| 210 | + mips-*-elf* | mips-*-rtems*) fmt=elf em=tmips ;; |
| 211 | mips-*-netbsd*) fmt=elf em=tmips ;; |
| 212 | mips-*-openbsd*) fmt=elf em=tmips ;; |
| 213 | |
| 214 | diff --git a/include/elf/mips.h b/include/elf/mips.h |
| 215 | index 57de3bc..9ba141d 100644 |
| 216 | --- a/include/elf/mips.h |
| 217 | +++ b/include/elf/mips.h |
| 218 | @@ -285,6 +285,7 @@ END_RELOC_NUMBERS (R_MIPS_maxext) |
| 219 | #define E_MIPS_MACH_SB1 0x008a0000 |
| 220 | #define E_MIPS_MACH_OCTEON 0x008b0000 |
| 221 | #define E_MIPS_MACH_XLR 0x008c0000 |
| 222 | +#define E_MIPS_MACH_XLP 0x008f0000 |
| 223 | #define E_MIPS_MACH_OCTEON2 0x008d0000 |
| 224 | #define E_MIPS_MACH_OCTEON3 0x008e0000 |
| 225 | #define E_MIPS_MACH_5400 0x00910000 |
| 226 | diff --git a/include/opcode/mips.h b/include/opcode/mips.h |
| 227 | index 9318fcc..9be5645 100644 |
| 228 | --- a/include/opcode/mips.h |
| 229 | +++ b/include/opcode/mips.h |
| 230 | @@ -1228,8 +1228,10 @@ static const unsigned int mips_isa_table[] = { |
| 231 | #define INSN_LOONGSON_2F 0x80000000 |
| 232 | /* Loongson 3A. */ |
| 233 | #define INSN_LOONGSON_3A 0x00000400 |
| 234 | -/* RMI Xlr instruction */ |
| 235 | -#define INSN_XLR 0x00000020 |
| 236 | +/* Netlogic Xlr instruction */ |
| 237 | +#define INSN_XLR 0x00000020 |
| 238 | +/* Netlogic XlP instruction */ |
| 239 | +#define INSN_XLP 0x00000080 |
| 240 | |
| 241 | /* DSP ASE */ |
| 242 | #define ASE_DSP 0x00000001 |
| 243 | @@ -1326,6 +1328,7 @@ static const unsigned int mips_isa_table[] = { |
| 244 | #define CPU_OCTEON2 6502 |
| 245 | #define CPU_OCTEON3 6503 |
| 246 | #define CPU_XLR 887682 /* decimal 'XLR' */ |
| 247 | +#define CPU_XLP 887680 /* decimal 'XLP' */ |
| 248 | |
| 249 | /* Return true if the given CPU is included in INSN_* mask MASK. */ |
| 250 | |
| 251 | @@ -1403,6 +1406,9 @@ cpu_is_member (int cpu, unsigned int mask) |
| 252 | return ((mask & INSN_ISA_MASK) == INSN_ISA32R6) |
| 253 | || ((mask & INSN_ISA_MASK) == INSN_ISA64R6); |
| 254 | |
| 255 | + case CPU_XLP: |
| 256 | + return (mask & INSN_XLP) != 0; |
| 257 | + |
| 258 | default: |
| 259 | return FALSE; |
| 260 | } |
| 261 | diff --git a/ld/configure.tgt b/ld/configure.tgt |
| 262 | index b45b1e5..fb2f36a 100644 |
| 263 | --- a/ld/configure.tgt |
| 264 | +++ b/ld/configure.tgt |
| 265 | @@ -495,6 +495,8 @@ mips*el-sde-elf*) targ_emul=elf32ltsmip |
| 266 | mips*-sde-elf* | mips*-mti-elf* | mips*-img-elf*) |
| 267 | targ_emul=elf32btsmip |
| 268 | targ_extra_emuls="elf32ltsmip elf32btsmipn32 elf64btsmip elf32ltsmipn32 elf64ltsmip" ;; |
| 269 | +mipsisa64*-*-elf*) targ_emul=elf32btsmip |
| 270 | + targ_extra_emuls="elf32ltsmip elf64btsmip elf64ltsmip" ;; |
| 271 | mips64*el-ps2-elf*) targ_emul=elf32lr5900n32 |
| 272 | targ_extra_emuls="elf32lr5900" |
| 273 | targ_extra_libpath=$targ_extra_emuls ;; |
| 274 | diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c |
| 275 | index 8200920..40d9fe2 100644 |
| 276 | --- a/opcodes/mips-dis.c |
| 277 | +++ b/opcodes/mips-dis.c |
| 278 | @@ -648,13 +648,11 @@ const struct mips_arch_choice mips_arch_choices[] = |
| 279 | mips_cp0sel_names_xlr, ARRAY_SIZE (mips_cp0sel_names_xlr), |
| 280 | mips_cp1_names_mips3264, mips_hwr_names_numeric }, |
| 281 | |
| 282 | - /* XLP is mostly like XLR, with the prominent exception it is being |
| 283 | - MIPS64R2. */ |
| 284 | - { "xlp", 1, bfd_mach_mips_xlr, CPU_XLR, |
| 285 | - ISA_MIPS64R2 | INSN_XLR, 0, |
| 286 | - mips_cp0_names_xlr, |
| 287 | - mips_cp0sel_names_xlr, ARRAY_SIZE (mips_cp0sel_names_xlr), |
| 288 | - mips_cp1_names_mips3264, mips_hwr_names_numeric }, |
| 289 | + { "xlp", 1, bfd_mach_mips_xlp, CPU_XLP, |
| 290 | + ISA_MIPS64R2 | INSN_XLP, 0, |
| 291 | + mips_cp0_names_mips3264r2, |
| 292 | + mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2), |
| 293 | + mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 }, |
| 294 | |
| 295 | /* This entry, mips16, is here only for ISA/processor selection; do |
| 296 | not print its name. */ |
| 297 | diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c |
| 298 | index 402f887..3764836 100644 |
| 299 | --- a/opcodes/mips-opc.c |
| 300 | +++ b/opcodes/mips-opc.c |
| 301 | @@ -320,7 +320,8 @@ decode_mips_operand (const char *p) |
| 302 | #define IOCTP (INSN_OCTEONP | INSN_OCTEON2 | INSN_OCTEON3) |
| 303 | #define IOCT2 (INSN_OCTEON2 | INSN_OCTEON3) |
| 304 | #define IOCT3 INSN_OCTEON3 |
| 305 | -#define XLR INSN_XLR |
| 306 | +#define XLR INSN_XLR |
| 307 | +#define XLP INSN_XLP |
| 308 | #define IVIRT ASE_VIRT |
| 309 | #define IVIRT64 ASE_VIRT64 |
| 310 | |
| 311 | @@ -957,6 +958,7 @@ const struct mips_opcode mips_builtin_opcodes[] = |
| 312 | {"clo", "U,s", 0x70000021, 0xfc0007ff, WR_1|RD_2, 0, I32|N55, 0, I37 }, |
| 313 | {"clz", "d,s", 0x00000050, 0xfc1f07ff, WR_1|RD_2, 0, I37, 0, 0 }, |
| 314 | {"clz", "U,s", 0x70000020, 0xfc0007ff, WR_1|RD_2, 0, I32|N55, 0, I37 }, |
| 315 | +{"crc", "d,s,t", 0x7000001c, 0xfc0007ff, WR_1|RD_2|RD_3, 0, XLP, 0, 0 }, |
| 316 | /* ctc0 is at the bottom of the table. */ |
| 317 | {"ctc1", "t,G", 0x44c00000, 0xffe007ff, RD_1|WR_CC|CM, 0, I1, 0, 0 }, |
| 318 | {"ctc1", "t,S", 0x44c00000, 0xffe007ff, RD_1|WR_CC|CM, 0, I1, 0, 0 }, |
| 319 | @@ -989,12 +991,13 @@ const struct mips_opcode mips_builtin_opcodes[] = |
| 320 | {"daddiu", "t,r,j", 0x64000000, 0xfc000000, WR_1|RD_2, 0, I3, 0, 0 }, |
| 321 | {"daddu", "d,v,t", 0x0000002d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I3, 0, 0 }, |
| 322 | {"daddu", "t,r,I", 0, (int) M_DADDU_I, INSN_MACRO, 0, I3, 0, 0 }, |
| 323 | -{"daddwc", "d,s,t", 0x70000038, 0xfc0007ff, WR_1|RD_2|RD_3|WR_C0|RD_C0, 0, XLR, 0, 0 }, |
| 324 | +{"daddwc", "d,s,t", 0x70000038, 0xfc0007ff, WR_1|RD_2|RD_3|WR_C0|RD_C0, 0, XLR|XLP, 0, 0 }, |
| 325 | {"dbreak", "", 0x7000003f, 0xffffffff, 0, 0, N5, 0, 0 }, |
| 326 | {"dclo", "d,s", 0x00000053, 0xfc1f07ff, WR_1|RD_2, 0, I69, 0, 0 }, |
| 327 | {"dclo", "U,s", 0x70000025, 0xfc0007ff, WR_1|RD_2, 0, I64|N55, 0, I69 }, |
| 328 | {"dclz", "d,s", 0x00000052, 0xfc1f07ff, WR_1|RD_2, 0, I69, 0, 0 }, |
| 329 | {"dclz", "U,s", 0x70000024, 0xfc0007ff, WR_1|RD_2, 0, I64|N55, 0, I69 }, |
| 330 | +{"dcrc", "d,s,t", 0x7000001d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, XLP, 0, 0 }, |
| 331 | /* dctr and dctw are used on the r5000. */ |
| 332 | {"dctr", "o(b)", 0xbc050000, 0xfc1f0000, RD_2, 0, I3, 0, 0 }, |
| 333 | {"dctw", "o(b)", 0xbc090000, 0xfc1f0000, RD_2, 0, I3, 0, 0 }, |
| 334 | @@ -1066,6 +1069,7 @@ const struct mips_opcode mips_builtin_opcodes[] = |
| 335 | {"dmfc0", "t,G,H", 0x40200000, 0xffe007f8, WR_1|RD_C0|LC, 0, I64, 0, 0 }, |
| 336 | {"dmfgc0", "t,G", 0x40600100, 0xffe007ff, WR_1|RD_C0|LC, 0, 0, IVIRT64, 0 }, |
| 337 | {"dmfgc0", "t,G,H", 0x40600100, 0xffe007f8, WR_1|RD_C0|LC, 0, 0, IVIRT64, 0 }, |
| 338 | +{"dmfur", "t,d", 0x7000001e, 0xffe007ff, WR_1, 0, XLP, 0, 0 }, |
| 339 | {"dmt", "", 0x41600bc1, 0xffffffff, TRAP, 0, 0, MT32, 0 }, |
| 340 | {"dmt", "t", 0x41600bc1, 0xffe0ffff, WR_1|TRAP, 0, 0, MT32, 0 }, |
| 341 | {"dmtc0", "t,G", 0x40a00000, 0xffe007ff, RD_1|WR_C0|WR_CC|CM, 0, I3, 0, EE }, |
| 342 | @@ -1081,6 +1085,8 @@ const struct mips_opcode mips_builtin_opcodes[] = |
| 343 | /* dmfc3 is at the bottom of the table. */ |
| 344 | /* dmtc3 is at the bottom of the table. */ |
| 345 | {"dmuh", "d,s,t", 0x000000dc, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I69, 0, 0 }, |
| 346 | +{"dmtur", "t,d", 0x7000001f, 0xffe007ff, RD_1, 0, XLP, 0, 0 }, |
| 347 | +{"dmul", "d,s,t", 0x70000006, 0xfc0007ff, WR_1|RD_2|RD_3, 0, XLP, 0, 0 }, |
| 348 | {"dmul", "d,s,t", 0x0000009c, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I69, 0, 0 }, |
| 349 | {"dmul", "d,v,t", 0x70000003, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, IOCT, 0, 0 }, |
| 350 | {"dmul", "d,v,t", 0, (int) M_DMUL, INSN_MACRO, 0, I3, 0, M32|I69 }, |
| 351 | @@ -1234,9 +1240,9 @@ const struct mips_opcode mips_builtin_opcodes[] = |
| 352 | {"ld", "s,-b(+R)", 0xec180000, 0xfc1c0000, WR_1, RD_pc, I69, 0, 0 }, |
| 353 | {"ld", "t,A(b)", 0, (int) M_LD_AB, INSN_MACRO, 0, I1, 0, 0 }, |
| 354 | {"ld", "t,o(b)", 0xdc000000, 0xfc000000, WR_1|RD_3|LM, 0, I3, 0, 0 }, |
| 355 | -{"ldaddw", "t,b", 0x70000010, 0xfc00ffff, MOD_1|RD_2|LM|SM, 0, XLR, 0, 0 }, |
| 356 | -{"ldaddwu", "t,b", 0x70000011, 0xfc00ffff, MOD_1|RD_2|LM|SM, 0, XLR, 0, 0 }, |
| 357 | -{"ldaddd", "t,b", 0x70000012, 0xfc00ffff, MOD_1|RD_2|LM|SM, 0, XLR, 0, 0 }, |
| 358 | +{"ldaddw", "t,b", 0x70000010, 0xfc00ffff, MOD_1|RD_2|SM, 0, XLR|XLP, 0, 0 }, |
| 359 | +{"ldaddwu", "t,b", 0x70000011, 0xfc00ffff, MOD_1|RD_2|SM, 0, XLR|XLP, 0, 0 }, |
| 360 | +{"ldaddd", "t,b", 0x70000012, 0xfc00ffff, MOD_1|RD_2|SM, 0, XLR|XLP, 0, 0 }, |
| 361 | {"ldc1", "T,o(b)", 0xd4000000, 0xfc000000, WR_1|RD_3|CLD|FP_D, 0, I2, 0, SF }, |
| 362 | {"ldc1", "E,o(b)", 0xd4000000, 0xfc000000, WR_1|RD_3|CLD|FP_D, 0, I2, 0, SF }, |
| 363 | {"ldc1", "T,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, INSN2_M_FP_D, I2, 0, SF }, |
| 364 | @@ -1401,7 +1407,7 @@ const struct mips_opcode mips_builtin_opcodes[] = |
| 365 | {"mflo", "d,9", 0x00000012, 0xff9f07ff, WR_1|RD_LO, 0, 0, D32, 0 }, |
| 366 | {"mflo1", "d", 0x70000012, 0xffff07ff, WR_1|RD_LO, 0, EE, 0, 0 }, |
| 367 | {"mflhxu", "d", 0x00000052, 0xffff07ff, WR_1|MOD_HILO, 0, 0, SMT, 0 }, |
| 368 | -{"mfcr", "t,s", 0x70000018, 0xfc00ffff, WR_1|RD_2, 0, XLR, 0, 0 }, |
| 369 | +{"mfcr", "t,s", 0x70000018, 0xfc00ffff, WR_1, 0, XLR|XLP, 0, 0 }, |
| 370 | {"mfsa", "d", 0x00000028, 0xffff07ff, WR_1, 0, EE, 0, 0 }, |
| 371 | {"min.ob", "X,Y,Q", 0x78000006, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 }, |
| 372 | {"min.ob", "D,S,Q", 0x48000006, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, N54, 0, 0 }, |
| 373 | @@ -1446,10 +1452,13 @@ const struct mips_opcode mips_builtin_opcodes[] = |
| 374 | /* move is at the top of the table. */ |
| 375 | {"msgn.qh", "X,Y,Q", 0x78200000, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 }, |
| 376 | {"msgsnd", "t", 0, (int) M_MSGSND, INSN_MACRO, 0, XLR, 0, 0 }, |
| 377 | +{"msgsnds", "d,t", 0x4a000001, 0xffe007ff, WR_1|RD_2|RD_C0|WR_C0, 0, XLP, 0, 0 }, |
| 378 | {"msgld", "", 0, (int) M_MSGLD, INSN_MACRO, 0, XLR, 0, 0 }, |
| 379 | {"msgld", "t", 0, (int) M_MSGLD_T, INSN_MACRO, 0, XLR, 0, 0 }, |
| 380 | -{"msgwait", "", 0, (int) M_MSGWAIT, INSN_MACRO, 0, XLR, 0, 0 }, |
| 381 | -{"msgwait", "t", 0, (int) M_MSGWAIT_T,INSN_MACRO, 0, XLR, 0, 0 }, |
| 382 | +{"msglds", "d,t", 0x4a000002, 0xffe007ff, WR_1|RD_2|RD_C0|WR_C0, 0, XLP, 0, 0 }, |
| 383 | +{"msgwait", "", 0, (int) M_MSGWAIT, INSN_MACRO, 0, XLR|XLP, 0, 0 }, |
| 384 | +{"msgwait", "t", 0, (int) M_MSGWAIT_T,INSN_MACRO, 0, XLR|XLP, 0, 0 }, |
| 385 | +{"msgsync", "", 0x4a000004, 0xffffffff,0, 0, XLP, 0, 0 }, |
| 386 | {"msub.d", "D,R,S,T", 0x4c000029, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0, I4_33, 0, I37 }, |
| 387 | {"msub.d", "D,S,T", 0x46200019, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, |
| 388 | {"msub.d", "D,S,T", 0x72200019, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F, 0, 0 }, |
| 389 | @@ -1499,7 +1508,7 @@ const struct mips_opcode mips_builtin_opcodes[] = |
| 390 | {"mtlo", "s,7", 0x00000013, 0xfc1fe7ff, RD_1|WR_LO, 0, 0, D32, 0 }, |
| 391 | {"mtlo1", "s", 0x70000013, 0xfc1fffff, RD_1|WR_LO, 0, EE, 0, 0 }, |
| 392 | {"mtlhx", "s", 0x00000053, 0xfc1fffff, RD_1|MOD_HILO, 0, 0, SMT, 0 }, |
| 393 | -{"mtcr", "t,s", 0x70000019, 0xfc00ffff, RD_1|RD_2, 0, XLR, 0, 0 }, |
| 394 | +{"mtcr", "t,s", 0x70000019, 0xfc00ffff, RD_1, 0, XLR|XLP, 0, 0 }, |
| 395 | {"mtm0", "s", 0x70000008, 0xfc1fffff, RD_1, 0, IOCT, 0, 0 }, |
| 396 | {"mtm0", "s,t", 0x70000008, 0xfc00ffff, RD_1|RD_2, 0, IOCT3, 0, 0 }, |
| 397 | {"mtm1", "s", 0x7000000c, 0xfc1fffff, RD_1, 0, IOCT, 0, 0 }, |
| 398 | @@ -1936,9 +1945,9 @@ const struct mips_opcode mips_builtin_opcodes[] = |
| 399 | {"suxc1", "S,t(b)", 0x4c00000d, 0xfc0007ff, RD_1|RD_2|RD_3|SM|FP_D, 0, I5_33|N55, 0, I37}, |
| 400 | {"sw", "t,o(b)", 0xac000000, 0xfc000000, RD_1|RD_3|SM, 0, I1, 0, 0 }, |
| 401 | {"sw", "t,A(b)", 0, (int) M_SW_AB, INSN_MACRO, 0, I1, 0, 0 }, |
| 402 | -{"swapw", "t,b", 0x70000014, 0xfc00ffff, MOD_1|RD_2|LM|SM, 0, XLR, 0, 0 }, |
| 403 | -{"swapwu", "t,b", 0x70000015, 0xfc00ffff, MOD_1|RD_2|LM|SM, 0, XLR, 0, 0 }, |
| 404 | -{"swapd", "t,b", 0x70000016, 0xfc00ffff, MOD_1|RD_2|LM|SM, 0, XLR, 0, 0 }, |
| 405 | +{"swapw", "t,b", 0x70000014, 0xfc00ffff, MOD_1|RD_2|SM, 0, XLR|XLP, 0, 0 }, |
| 406 | +{"swapwu", "t,b", 0x70000015, 0xfc00ffff, MOD_1|RD_2|SM, 0, XLR|XLP, 0, 0 }, |
| 407 | +{"swapd", "t,b", 0x70000016, 0xfc00ffff, MOD_1|RD_2|SM, 0, XLR|XLP, 0, 0 }, |
| 408 | {"swc0", "E,o(b)", 0xe0000000, 0xfc000000, RD_3|RD_C0|SM, 0, I1, 0, IOCT|IOCTP|IOCT2|I37 }, |
| 409 | {"swc0", "E,A(b)", 0, (int) M_SWC0_AB, INSN_MACRO, 0, I1, 0, IOCT|IOCTP|IOCT2|I37 }, |
| 410 | {"swc1", "T,o(b)", 0xe4000000, 0xfc000000, RD_1|RD_3|SM|FP_S, 0, I1, 0, 0 }, |
| 411 | -- |
| 412 | 2.7.1 |
| 413 | |