| Thang Q. Nguyen | 7d0f84a | 2021-09-23 06:47:52 +0000 | [diff] [blame] | 1 | #!/bin/bash |
| 2 | |
| Patrick Williams | 0731ef8 | 2023-04-16 16:41:45 -0500 | [diff] [blame] | 3 | # shellcheck source=meta-ampere/meta-jade/recipes-ampere/platform/ampere-utils/gpio-lib.sh |
| Thang Q. Nguyen | 7d0f84a | 2021-09-23 06:47:52 +0000 | [diff] [blame] | 4 | source /usr/sbin/gpio-lib.sh |
| Patrick Williams | 0731ef8 | 2023-04-16 16:41:45 -0500 | [diff] [blame] | 5 | # shellcheck source=meta-ampere/meta-jade/recipes-ampere/platform/ampere-utils/gpio-defs.sh |
| Thang Q. Nguyen | bddca60 | 2022-07-29 14:45:33 +0700 | [diff] [blame] | 6 | source /usr/sbin/gpio-defs.sh |
| Chau Ly | 0a0f348 | 2023-04-13 05:06:28 +0000 | [diff] [blame] | 7 | source /usr/sbin/ampere_uart_console_setup.sh |
| Thang Q. Nguyen | 7d0f84a | 2021-09-23 06:47:52 +0000 | [diff] [blame] | 8 | |
| Thang Q. Nguyen | bddca60 | 2022-07-29 14:45:33 +0700 | [diff] [blame] | 9 | # Configure to boot from MAIN SPI-HOST |
| 10 | gpio_configure_output "$SPI0_BACKUP_SEL" 0 |
| Thang Q. Nguyen | 7d0f84a | 2021-09-23 06:47:52 +0000 | [diff] [blame] | 11 | |
| Thang Q. Nguyen | bddca60 | 2022-07-29 14:45:33 +0700 | [diff] [blame] | 12 | gpio_configure_input "$S0_I2C9_ALERT_L" |
| 13 | gpio_configure_input "$S1_I2C9_ALERT_L" |
| 14 | gpio_configure_input "$GPIO_BMC_VGA_FRONT_PRES_L" |
| 15 | gpio_configure_input "$GPIO_S0_VRHOT_L" |
| 16 | gpio_configure_input "$GPIO_S1_VRHOT_L" |
| 17 | gpio_configure_output "$BMC_VGA_SEL" 1 |
| Thang Q. Nguyen | 7d0f84a | 2021-09-23 06:47:52 +0000 | [diff] [blame] | 18 | |
| 19 | # ======================================================= |
| 20 | # Below GPIOs are controlled by other services so just |
| 21 | # initialize in A/C power only. |
| Thang Q. Nguyen | ed81813 | 2022-02-22 10:48:32 +0000 | [diff] [blame] | 22 | bootstatus=$(cat /sys/class/watchdog/watchdog0/bootstatus) |
| 23 | if [ "$bootstatus" == '32' ]; then |
| Thang Q. Nguyen | bddca60 | 2022-07-29 14:45:33 +0700 | [diff] [blame] | 24 | gpio_configure_output "$BMC_GPIOR2_EXT_HIGHTEMP_L" 1 |
| 25 | gpio_configure_output "$GPIO_BMC_VR_PMBUS_SEL_L" 1 |
| 26 | gpio_configure_output "$GPIO_BMC_I2C6_RESET_L" 1 |
| Thang Q. Nguyen | 7d0f84a | 2021-09-23 06:47:52 +0000 | [diff] [blame] | 27 | |
| Thang Q. Nguyen | bddca60 | 2022-07-29 14:45:33 +0700 | [diff] [blame] | 28 | # Initialize OCP register |
| 29 | gpio_configure_output "$OCP_MAIN_PWREN" 0 |
| Thang Q. Nguyen | 7d0f84a | 2021-09-23 06:47:52 +0000 | [diff] [blame] | 30 | |
| Thang Q. Nguyen | bddca60 | 2022-07-29 14:45:33 +0700 | [diff] [blame] | 31 | # Configure SPI-NOR/EEPROM switching |
| 32 | gpio_configure_output "$SPI0_PROGRAM_SEL" 0 |
| 33 | gpio_configure_output "$BMC_I2C_BACKUP_SEL" 1 |
| 34 | gpio_configure_output "$SPI0_BACKUP_SEL" 0 |
| Thang Q. Nguyen | 7d0f84a | 2021-09-23 06:47:52 +0000 | [diff] [blame] | 35 | |
| Thang Q. Nguyen | bddca60 | 2022-07-29 14:45:33 +0700 | [diff] [blame] | 36 | # Initialize BMC_SYS_PSON_L, SHD_REQ_L, BMC_SYSRESET_L |
| 37 | gpio_configure_output "$SYS_PSON_L" 1 |
| 38 | gpio_configure_output "$S0_SHD_REQ_L" 1 |
| 39 | gpio_configure_output "$S0_SYSRESET_L" 1 |
| 40 | gpio_configure_output "$S1_SYSRESET_L" 1 |
| Thang Q. Nguyen | 7d0f84a | 2021-09-23 06:47:52 +0000 | [diff] [blame] | 41 | |
| Thang Q. Nguyen | bddca60 | 2022-07-29 14:45:33 +0700 | [diff] [blame] | 42 | # RTC Lock, SPECIAL_BOOT |
| 43 | gpio_configure_output "$RTC_LOCK" 0 |
| 44 | gpio_configure_output "$S0_SPECIAL_BOOT" 0 |
| 45 | gpio_configure_output "$S1_SPECIAL_BOOT" 0 |
| Thang Q. Nguyen | 7d0f84a | 2021-09-23 06:47:52 +0000 | [diff] [blame] | 46 | fi |
| Thang Q. Nguyen | bddca60 | 2022-07-29 14:45:33 +0700 | [diff] [blame] | 47 | |
| 48 | gpio_configure_output "$BMC_READY" 1 |
| Chau Ly | 0a0f348 | 2023-04-13 05:06:28 +0000 | [diff] [blame] | 49 | # ======================================================= |
| 50 | # Setting uart muxes to BMC as default |
| 51 | uart_console_setup |