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Ben Tyner92e39fd2020-02-05 18:11:02 -06001/**
Ben Tynerb859d792020-05-06 21:29:47 -05002 * @file These are the implementations of the user interfaces declared
3 * in hei_user_interface.hpp
Ben Tyner92e39fd2020-02-05 18:11:02 -06004 */
5
Ben Tynerb859d792020-05-06 21:29:47 -05006#include <assert.h>
Ben Tyner0523f8a2020-05-14 16:01:53 -05007#include <inttypes.h>
8#include <libpdbg.h>
Zane Shelleyb78dd0c2020-05-08 14:35:15 -05009#include <stdarg.h>
10#include <stdio.h>
11
Ben Tyner92e39fd2020-02-05 18:11:02 -060012#include <hei_user_interface.hpp>
Zane Shelleya0299852020-11-13 13:38:04 -060013#include <util/pdbg.hpp>
Zane Shelley0c44c2f2020-06-05 17:14:31 -050014#include <util/trace.hpp>
Ben Tyner92e39fd2020-02-05 18:11:02 -060015
16namespace libhei
17{
18
Zane Shelley06e10f92020-08-10 20:35:08 -050019const char* __regType(RegisterType_t i_regType)
20{
21 const char* str = "";
22 switch (i_regType)
23 {
24 case REG_TYPE_SCOM:
25 str = "SCOM";
26 break;
27 case REG_TYPE_ID_SCOM:
28 str = "ID_SCOM";
29 break;
30 default:
31 trace::err("Unsupported register type: i_regType=0x%02x",
32 i_regType);
33 assert(0);
34 }
35 return str;
36}
37
38//------------------------------------------------------------------------------
39
40bool __readProc(pdbg_target* i_procTrgt, RegisterType_t i_regType,
41 uint64_t i_address, uint64_t& o_value)
42{
43 bool accessFailure = false;
44
45 // The processor PIB target is required for SCOM access.
Zane Shelley171a2e02020-11-13 13:56:13 -060046 pdbg_target* scomTrgt = util::pdbg::getPibTrgt(i_procTrgt);
Zane Shelley06e10f92020-08-10 20:35:08 -050047
48 switch (i_regType)
49 {
50 case REG_TYPE_SCOM:
51 case REG_TYPE_ID_SCOM:
52 // Read the 64-bit SCOM register.
53 accessFailure = (0 != pib_read(scomTrgt, i_address, &o_value));
54 break;
55
56 default:
57 trace::err("Unsupported register type: trgt=%s regType=0x%02x "
58 "addr=0x%0" PRIx64,
Zane Shelleya0299852020-11-13 13:38:04 -060059 util::pdbg::getPath(i_procTrgt), i_regType, i_address);
Zane Shelley06e10f92020-08-10 20:35:08 -050060 assert(0); // an unsupported register type
61 }
62
63 return accessFailure;
64}
65
66//------------------------------------------------------------------------------
67
Zane Shelley1d29e5c2021-03-17 13:51:02 -050068bool __readOcmb(pdbg_target* i_obmcTrgt, RegisterType_t i_regType,
69 uint64_t i_address, uint64_t& o_value)
Zane Shelley06e10f92020-08-10 20:35:08 -050070{
71 bool accessFailure = false;
72
Zane Shelley06e10f92020-08-10 20:35:08 -050073 // The OCMB target is used for SCOM access.
74 pdbg_target* scomTrgt = i_obmcTrgt;
75
76 switch (i_regType)
77 {
78 case REG_TYPE_SCOM:
79 case REG_TYPE_ID_SCOM:
80 // Read the 64-bit SCOM register.
81 accessFailure = (0 != ocmb_getscom(scomTrgt, i_address, &o_value));
82 break;
83
84 default:
85 trace::err("Unsupported register type: trgt=%s regType=0x%02x "
86 "addr=0x%0" PRIx64,
Zane Shelleya0299852020-11-13 13:38:04 -060087 util::pdbg::getPath(i_obmcTrgt), i_regType, i_address);
Zane Shelley06e10f92020-08-10 20:35:08 -050088 assert(0);
89 }
Zane Shelley06e10f92020-08-10 20:35:08 -050090
91 return accessFailure;
92}
93
Ben Tyner92e39fd2020-02-05 18:11:02 -060094//------------------------------------------------------------------------------
95
Ben Tyner0523f8a2020-05-14 16:01:53 -050096bool registerRead(const Chip& i_chip, RegisterType_t i_regType,
97 uint64_t i_address, uint64_t& o_value)
Ben Tyner92e39fd2020-02-05 18:11:02 -060098{
Zane Shelleyb78dd0c2020-05-08 14:35:15 -050099 bool accessFailure = false;
Ben Tyner92e39fd2020-02-05 18:11:02 -0600100
Zane Shelleya0299852020-11-13 13:38:04 -0600101 auto trgt = util::pdbg::getTrgt(i_chip);
Zane Shelley2f263182020-07-10 21:41:21 -0500102
Zane Shelleya0299852020-11-13 13:38:04 -0600103 uint8_t trgtType = util::pdbg::getTrgtType(trgt);
Zane Shelley06e10f92020-08-10 20:35:08 -0500104
105 switch (trgtType)
Ben Tyner0523f8a2020-05-14 16:01:53 -0500106 {
Zane Shelley06e10f92020-08-10 20:35:08 -0500107 case 0x05: // PROC
108 accessFailure = __readProc(trgt, i_regType, i_address, o_value);
109 break;
110
111 case 0x4b: // OCMB_CHIP
112 accessFailure = __readOcmb(trgt, i_regType, i_address, o_value);
Ben Tyner0523f8a2020-05-14 16:01:53 -0500113 break;
Ben Tynerb859d792020-05-06 21:29:47 -0500114
Ben Tyner0523f8a2020-05-14 16:01:53 -0500115 default:
Zane Shelley06e10f92020-08-10 20:35:08 -0500116 trace::err("Unsupported target type: trgt=%s trgtType=0x%02x",
Zane Shelleya0299852020-11-13 13:38:04 -0600117 util::pdbg::getPath(trgt), trgtType);
Zane Shelley06e10f92020-08-10 20:35:08 -0500118 assert(0);
Ben Tyner0523f8a2020-05-14 16:01:53 -0500119 }
120
121 if (accessFailure)
122 {
Zane Shelley06e10f92020-08-10 20:35:08 -0500123 trace::err("%s failure: trgt=%s addr=0x%0" PRIx64, __regType(i_regType),
Zane Shelleya0299852020-11-13 13:38:04 -0600124 util::pdbg::getPath(trgt), i_address);
Ben Tyner0523f8a2020-05-14 16:01:53 -0500125 o_value = 0; // just in case
126 }
Ben Tyner92e39fd2020-02-05 18:11:02 -0600127
Zane Shelleyb78dd0c2020-05-08 14:35:15 -0500128 return accessFailure;
Ben Tyner92e39fd2020-02-05 18:11:02 -0600129}
130
131//------------------------------------------------------------------------------
132
Zane Shelleyb78dd0c2020-05-08 14:35:15 -0500133// prints a single line to stdout
134void hei_inf(char* format, ...)
135{
136 va_list args;
Zane Shelleyb78dd0c2020-05-08 14:35:15 -0500137 va_start(args, format);
Zane Shelley0c44c2f2020-06-05 17:14:31 -0500138 trace::inf(format, args);
Zane Shelleyb78dd0c2020-05-08 14:35:15 -0500139 va_end(args);
Zane Shelleyb78dd0c2020-05-08 14:35:15 -0500140}
141
142//------------------------------------------------------------------------------
143
144// prints a single line to stderr
145void hei_err(char* format, ...)
146{
147 va_list args;
Zane Shelleyb78dd0c2020-05-08 14:35:15 -0500148 va_start(args, format);
Zane Shelley0c44c2f2020-06-05 17:14:31 -0500149 trace::err(format, args);
Zane Shelleyb78dd0c2020-05-08 14:35:15 -0500150 va_end(args);
Zane Shelleyb78dd0c2020-05-08 14:35:15 -0500151}
152
Ben Tyner92e39fd2020-02-05 18:11:02 -0600153} // namespace libhei