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Ben Tyner92e39fd2020-02-05 18:11:02 -06001/**
Ben Tynerb859d792020-05-06 21:29:47 -05002 * @file These are the implementations of the user interfaces declared
3 * in hei_user_interface.hpp
Ben Tyner92e39fd2020-02-05 18:11:02 -06004 */
5
Ben Tynerb859d792020-05-06 21:29:47 -05006#include <assert.h>
Ben Tyner0523f8a2020-05-14 16:01:53 -05007#include <inttypes.h>
8#include <libpdbg.h>
Zane Shelleyb78dd0c2020-05-08 14:35:15 -05009#include <stdarg.h>
10#include <stdio.h>
11
Ben Tyner92e39fd2020-02-05 18:11:02 -060012#include <hei_user_interface.hpp>
Zane Shelley0c44c2f2020-06-05 17:14:31 -050013#include <util/trace.hpp>
Ben Tyner92e39fd2020-02-05 18:11:02 -060014
15namespace libhei
16{
17
Zane Shelley06e10f92020-08-10 20:35:08 -050018const char* __regType(RegisterType_t i_regType)
19{
20 const char* str = "";
21 switch (i_regType)
22 {
23 case REG_TYPE_SCOM:
24 str = "SCOM";
25 break;
26 case REG_TYPE_ID_SCOM:
27 str = "ID_SCOM";
28 break;
29 default:
30 trace::err("Unsupported register type: i_regType=0x%02x",
31 i_regType);
32 assert(0);
33 }
34 return str;
35}
36
37//------------------------------------------------------------------------------
38
39bool __readProc(pdbg_target* i_procTrgt, RegisterType_t i_regType,
40 uint64_t i_address, uint64_t& o_value)
41{
42 bool accessFailure = false;
43
44 // The processor PIB target is required for SCOM access.
45 char path[16];
46 sprintf(path, "/proc%d/pib", pdbg_target_index(i_procTrgt));
47 pdbg_target* scomTrgt = pdbg_target_from_path(nullptr, path);
48 assert(nullptr != scomTrgt);
49
50 switch (i_regType)
51 {
52 case REG_TYPE_SCOM:
53 case REG_TYPE_ID_SCOM:
54 // Read the 64-bit SCOM register.
55 accessFailure = (0 != pib_read(scomTrgt, i_address, &o_value));
56 break;
57
58 default:
59 trace::err("Unsupported register type: trgt=%s regType=0x%02x "
60 "addr=0x%0" PRIx64,
61 pdbg_target_path(i_procTrgt), i_regType, i_address);
62 assert(0); // an unsupported register type
63 }
64
65 return accessFailure;
66}
67
68//------------------------------------------------------------------------------
69
70bool __readOcmb(pdbg_target* i_obmcTrgt, RegisterType_t i_regType,
71 uint64_t i_address, uint64_t& o_value)
72{
73 bool accessFailure = false;
74
75 /* TODO: ocmb_getscom() currently does not exist upstream.
76 // The OCMB target is used for SCOM access.
77 pdbg_target* scomTrgt = i_obmcTrgt;
78
79 switch (i_regType)
80 {
81 case REG_TYPE_SCOM:
82 case REG_TYPE_ID_SCOM:
83 // Read the 64-bit SCOM register.
84 accessFailure = (0 != ocmb_getscom(scomTrgt, i_address, &o_value));
85 break;
86
87 default:
88 trace::err("Unsupported register type: trgt=%s regType=0x%02x "
89 "addr=0x%0" PRIx64,
90 pdbg_target_path(i_obmcTrgt), i_regType, i_address);
91 assert(0);
92 }
93 */
94
95 return accessFailure;
96}
97
Ben Tyner92e39fd2020-02-05 18:11:02 -060098//------------------------------------------------------------------------------
99
Ben Tyner0523f8a2020-05-14 16:01:53 -0500100bool registerRead(const Chip& i_chip, RegisterType_t i_regType,
101 uint64_t i_address, uint64_t& o_value)
Ben Tyner92e39fd2020-02-05 18:11:02 -0600102{
Zane Shelleyb78dd0c2020-05-08 14:35:15 -0500103 bool accessFailure = false;
Ben Tyner92e39fd2020-02-05 18:11:02 -0600104
Zane Shelley2f263182020-07-10 21:41:21 -0500105 auto trgt = (pdbg_target*)(i_chip.getChip());
106
Zane Shelley06e10f92020-08-10 20:35:08 -0500107 uint8_t trgtType = 0;
108 pdbg_target_get_attribute(trgt, "ATTR_TYPE", 1, 1, &trgtType);
109
110 switch (trgtType)
Ben Tyner0523f8a2020-05-14 16:01:53 -0500111 {
Zane Shelley06e10f92020-08-10 20:35:08 -0500112 case 0x05: // PROC
113 accessFailure = __readProc(trgt, i_regType, i_address, o_value);
114 break;
115
116 case 0x4b: // OCMB_CHIP
117 accessFailure = __readOcmb(trgt, i_regType, i_address, o_value);
Ben Tyner0523f8a2020-05-14 16:01:53 -0500118 break;
Ben Tynerb859d792020-05-06 21:29:47 -0500119
Ben Tyner0523f8a2020-05-14 16:01:53 -0500120 default:
Zane Shelley06e10f92020-08-10 20:35:08 -0500121 trace::err("Unsupported target type: trgt=%s trgtType=0x%02x",
122 pdbg_target_path(trgt), trgtType);
123 assert(0);
Ben Tyner0523f8a2020-05-14 16:01:53 -0500124 }
125
126 if (accessFailure)
127 {
Zane Shelley06e10f92020-08-10 20:35:08 -0500128 trace::err("%s failure: trgt=%s addr=0x%0" PRIx64, __regType(i_regType),
129 pdbg_target_path(trgt), i_address);
Ben Tyner0523f8a2020-05-14 16:01:53 -0500130 o_value = 0; // just in case
131 }
Ben Tyner92e39fd2020-02-05 18:11:02 -0600132
Zane Shelleyb78dd0c2020-05-08 14:35:15 -0500133 return accessFailure;
Ben Tyner92e39fd2020-02-05 18:11:02 -0600134}
135
136//------------------------------------------------------------------------------
137
Zane Shelleyb78dd0c2020-05-08 14:35:15 -0500138// prints a single line to stdout
139void hei_inf(char* format, ...)
140{
141 va_list args;
Zane Shelleyb78dd0c2020-05-08 14:35:15 -0500142 va_start(args, format);
Zane Shelley0c44c2f2020-06-05 17:14:31 -0500143 trace::inf(format, args);
Zane Shelleyb78dd0c2020-05-08 14:35:15 -0500144 va_end(args);
Zane Shelleyb78dd0c2020-05-08 14:35:15 -0500145}
146
147//------------------------------------------------------------------------------
148
149// prints a single line to stderr
150void hei_err(char* format, ...)
151{
152 va_list args;
Zane Shelleyb78dd0c2020-05-08 14:35:15 -0500153 va_start(args, format);
Zane Shelley0c44c2f2020-06-05 17:14:31 -0500154 trace::err(format, args);
Zane Shelleyb78dd0c2020-05-08 14:35:15 -0500155 va_end(args);
Zane Shelleyb78dd0c2020-05-08 14:35:15 -0500156}
157
Ben Tyner92e39fd2020-02-05 18:11:02 -0600158} // namespace libhei