commit 941193382242f27409a28d68adae9b7e0bd7b598
author Zane Shelley <zshelle@us.ibm.com> Wed Sep 22 15:00:43 2021 -0500
committer Zane Shelley <zshelle@us.ibm.com> Wed Sep 22 15:01:25 2021 -0500
tree 06b59595ca1b7f3a04f4d8f1e47170ae90584dc9
parent 2a3b925b8c190c5977f1341aecceb50279b82572

Fix signature descriptions for chiplet FIRs

Signed-off-by: Zane Shelley <zshelle@us.ibm.com>
Change-Id: Ia997666829269597ee87aa0685499badc86b83ba

xml/p10/node_cfir_n0_cs_re.xml

diff --git a/xml/p10/node_cfir_n0_cs_re.xml b/xml/p10/node_cfir_n0_cs_re.xml
index 845b897..7a24f09 100644
--- a/xml/p10/node_cfir_n0_cs_re.xml
+++ b/xml/p10/node_cfir_n0_cs_re.xml
@@ -30,14 +30,14 @@
             <expr type="int" value1="0x0FFFFFFFFFFFFFFF"/>
         </expr>
     </rule>
-    <bit child_node="N0_LOCAL_FIR" node_inst="0" pos="4">Local FIR</bit>
-    <bit child_node="NMMU_CQ_FIR" node_inst="0" pos="5">PBI CQ FIR Register</bit>
-    <bit child_node="NMMU_FIR" node_inst="0" pos="6">NMMU FIR1 Register</bit>
-    <bit child_node="INT_CQ_FIR" node_inst="0" pos="7">Primary Error Register for INT_CQ.  This contains all of the individual errors detected by INT_CQ, plus summary error indicators from VC and PC (see bits 43:63).</bit>
-    <bit child_node="VAS_FIR" node_inst="0" pos="8">Local FIR register for the VAS unit logic</bit>
-    <bit child_node="NX_DMA_ENG_FIR" node_inst="0" pos="9">DMA and Engine Fault Isolation Register</bit>
-    <bit child_node="NX_CQ_FIR" node_inst="0" pos="10">PBI CQ FIR Register</bit>
-    <bit child_node="PCI_NEST_FIR" node_inst="3" pos="13">PCI Nest FIR Register</bit>
-    <bit child_node="PCI_NEST_FIR" node_inst="4" pos="14">PCI Nest FIR Register</bit>
-    <bit child_node="PCI_NEST_FIR" node_inst="5" pos="15">PCI Nest FIR Register</bit>
+    <bit child_node="N0_LOCAL_FIR" node_inst="0" pos="4">Attention from N0_LOCAL_FIR</bit>
+    <bit child_node="NMMU_CQ_FIR" node_inst="0" pos="5">Attention from NMMU_CQ_FIR 0</bit>
+    <bit child_node="NMMU_FIR" node_inst="0" pos="6">Attention from NMMU_FIR 0</bit>
+    <bit child_node="INT_CQ_FIR" node_inst="0" pos="7">Attention from INT_CQ_FIR</bit>
+    <bit child_node="VAS_FIR" node_inst="0" pos="8">Attention from VAS_FIR</bit>
+    <bit child_node="NX_DMA_ENG_FIR" node_inst="0" pos="9">Attention from NX_DMA_ENG_FIR</bit>
+    <bit child_node="NX_CQ_FIR" node_inst="0" pos="10">Attention from NX_CQ_FIR</bit>
+    <bit child_node="PCI_NEST_FIR" node_inst="3" pos="13">Attention from PCI_NEST_FIR 3</bit>
+    <bit child_node="PCI_NEST_FIR" node_inst="4" pos="14">Attention from PCI_NEST_FIR 4</bit>
+    <bit child_node="PCI_NEST_FIR" node_inst="5" pos="15">Attention from PCI_NEST_FIR 5</bit>
 </attn_node>