Update chip data files with new write operation rules
Signed-off-by: Caleb Palmer <cnpalmer@us.ibm.com>
Change-Id: Ide9bad598dbf8c766632c840f4c4c3f8a882bc3e
diff --git a/chip_data/chip-data-json.md b/chip_data/chip-data-json.md
index 38872c6..5918689 100644
--- a/chip_data/chip-data-json.md
+++ b/chip_data/chip-data-json.md
@@ -196,6 +196,18 @@
files for additional debug, if necessary. The array is used to maintain the
order in which registers are captured and stored in the FFDC.
+### 3.5) Property: `op_rules` (optional, object)
+
+A JSON object where the keys are operation types as defined in the table below
+and the values are Operation Rule JSON objects.
+
+| Value | Description |
+| ------------ | ------------------------------------------ |
+| `FIR_SET` | Operation to set a bit in the FIR |
+| `FIR_CLEAR` | Operation to clear a bit in the FIR |
+| `MASK_SET` | Operation to set a bit in the FIR's mask |
+| `MASK_CLEAR` | Operation to clear a bit in the FIR's mask |
+
---
## 4) Isolation Rule JSON Object
@@ -437,6 +449,30 @@
**Important:** If a group instance is not defined in this map, the register
simply will not be captured.
+## 10) Operation Rule JSON Object
+
+The object describes the operation and register required to perform some write
+operation to a FIR. The operation to be performed is specified by the key value
+of the `op_rules` property of a Isolation Node JSON object.
+
+### 11.1) Property: `op_rule` (required, string)
+
+A string used to describe what action will need to be taken to write the
+indicated register.
+
+| Value | Description |
+| ------------------ | ------------------------------------------------------- |
+| `atomic_or` | Treat indicated reg as an atomic OR reg to set a bit |
+| `atomic_and` | Treat indicated reg as an atomic AND reg to clear a bit |
+| `read_set_write` | Read, modify, write indicated reg to set a bit |
+| `read_clear_write` | Read, modify, write indicated reg to clear a bit |
+
+### 11.2) Property: `reg_name` (required, string)
+
+A string used to indicate the register to be written to perform the desired
+write operation to the FIR or it's mask. The name of the register should match a
+register defined in the `registers` property of the Base JSON Object.
+
---
## 10) Appendix
diff --git a/chip_data/explorer/chip_explorer.json b/chip_data/explorer/chip_explorer.json
index 1d6f606..897218a 100644
--- a/chip_data/explorer/chip_explorer.json
+++ b/chip_data/explorer/chip_explorer.json
@@ -3,11 +3,11 @@
"model_ec": ["EXPLORER_11", "EXPLORER_20"],
"root_nodes": {
"CHIP_CS": {
- "name": "CHIPLET_OCMB_FIR",
+ "name": "CHIPLET_OCMB_FIR_CHIP_CS",
"inst": 0
},
"RECOV": {
- "name": "CHIPLET_OCMB_FIR",
+ "name": "CHIPLET_OCMB_FIR_RECOV",
"inst": 0
},
"SP_ATTN": {
diff --git a/chip_data/explorer/node_chiplet_ocmb_fir.json b/chip_data/explorer/node_chiplet_ocmb_fir.json
index 9217105..1fa102f 100644
--- a/chip_data/explorer/node_chiplet_ocmb_fir.json
+++ b/chip_data/explorer/node_chiplet_ocmb_fir.json
@@ -19,7 +19,7 @@
}
},
"isolation_nodes": {
- "CHIPLET_OCMB_FIR": {
+ "CHIPLET_OCMB_FIR_CHIP_CS": {
"instances": [0],
"rules": [
{
@@ -45,7 +45,66 @@
}
]
}
+ }
+ ],
+ "op_rules": {
+ "MASK_SET": {
+ "op_rule": "read_set_write",
+ "reg_name": "CHIPLET_OCMB_FIR_MASK"
},
+ "MASK_CLEAR": {
+ "op_rule": "read_clear_write",
+ "reg_name": "CHIPLET_OCMB_FIR_MASK"
+ }
+ },
+ "bits": {
+ "3": {
+ "desc": "Attention from OCMB_LFIR",
+ "child_node": {
+ "name": "OCMB_LFIR"
+ }
+ },
+ "4": {
+ "desc": "Attention from MMIOFIR",
+ "child_node": {
+ "name": "MMIOFIR"
+ }
+ },
+ "7": {
+ "desc": "Attention from SRQFIR",
+ "child_node": {
+ "name": "SRQFIR"
+ }
+ },
+ "8": {
+ "desc": "Attention from MCBISTFIR",
+ "child_node": {
+ "name": "MCBISTFIR"
+ }
+ },
+ "9": {
+ "desc": "Attention from RDFFIR",
+ "child_node": {
+ "name": "RDFFIR"
+ }
+ },
+ "11": {
+ "desc": "Attention from TLXFIR",
+ "child_node": {
+ "name": "TLXFIR"
+ }
+ },
+ "12": {
+ "desc": "Attention from OMI_DL_FIR",
+ "child_node": {
+ "name": "OMI_DL_FIR"
+ }
+ }
+ }
+ },
+ "CHIPLET_OCMB_FIR_RECOV": {
+ "instances": [0],
+ "rules": [
{
"attn_type": ["RECOV"],
"node_inst": [0],
@@ -75,6 +134,16 @@
}
}
],
+ "op_rules": {
+ "MASK_SET": {
+ "op_rule": "read_set_write",
+ "reg_name": "CHIPLET_OCMB_FIR_MASK"
+ },
+ "MASK_CLEAR": {
+ "op_rule": "read_clear_write",
+ "reg_name": "CHIPLET_OCMB_FIR_MASK"
+ }
+ },
"bits": {
"3": {
"desc": "Attention from OCMB_LFIR",
diff --git a/chip_data/explorer/node_chiplet_ocmb_spa_fir.json b/chip_data/explorer/node_chiplet_ocmb_spa_fir.json
index 4465e69..f8771f9 100644
--- a/chip_data/explorer/node_chiplet_ocmb_spa_fir.json
+++ b/chip_data/explorer/node_chiplet_ocmb_spa_fir.json
@@ -38,6 +38,16 @@
}
}
],
+ "op_rules": {
+ "MASK_SET": {
+ "op_rule": "read_set_write",
+ "reg_name": "CHIPLET_OCMB_SPA_FIR_MASK"
+ },
+ "MASK_CLEAR": {
+ "op_rule": "read_clear_write",
+ "reg_name": "CHIPLET_OCMB_SPA_FIR_MASK"
+ }
+ },
"bits": {
"1": {
"desc": "Attention from MMIOFIR",
diff --git a/chip_data/explorer/node_mcbistfir.json b/chip_data/explorer/node_mcbistfir.json
index 666e57c..e70af77 100644
--- a/chip_data/explorer/node_mcbistfir.json
+++ b/chip_data/explorer/node_mcbistfir.json
@@ -7,11 +7,35 @@
"0": "0x08011800"
}
},
+ "MCBISTFIR_AND": {
+ "access": "WO",
+ "instances": {
+ "0": "0x08011801"
+ }
+ },
+ "MCBISTFIR_OR": {
+ "access": "WO",
+ "instances": {
+ "0": "0x08011802"
+ }
+ },
"MCBISTFIR_MASK": {
"instances": {
"0": "0x08011803"
}
},
+ "MCBISTFIR_MASK_AND": {
+ "access": "WO",
+ "instances": {
+ "0": "0x08011804"
+ }
+ },
+ "MCBISTFIR_MASK_OR": {
+ "access": "WO",
+ "instances": {
+ "0": "0x08011805"
+ }
+ },
"MCBISTFIR_ACT0": {
"instances": {
"0": "0x08011806"
@@ -139,6 +163,24 @@
}
}
],
+ "op_rules": {
+ "FIR_SET": {
+ "op_rule": "atomic_or",
+ "reg_name": "MCBISTFIR_OR"
+ },
+ "FIR_CLEAR": {
+ "op_rule": "atomic_and",
+ "reg_name": "MCBISTFIR_AND"
+ },
+ "MASK_SET": {
+ "op_rule": "atomic_or",
+ "reg_name": "MCBISTFIR_MASK_OR"
+ },
+ "MASK_CLEAR": {
+ "op_rule": "atomic_and",
+ "reg_name": "MCBISTFIR_MASK_AND"
+ }
+ },
"bits": {
"0": {
"desc": "Invalid maint address"
diff --git a/chip_data/explorer/node_mmiofir.json b/chip_data/explorer/node_mmiofir.json
index d0a0824..7aa501d 100644
--- a/chip_data/explorer/node_mmiofir.json
+++ b/chip_data/explorer/node_mmiofir.json
@@ -7,11 +7,35 @@
"0": "0x08010870"
}
},
+ "MMIOFIR_AND": {
+ "access": "WO",
+ "instances": {
+ "0": "0x08010871"
+ }
+ },
+ "MMIOFIR_OR": {
+ "access": "WO",
+ "instances": {
+ "0": "0x08010872"
+ }
+ },
"MMIOFIR_MASK": {
"instances": {
"0": "0x08010873"
}
},
+ "MMIOFIR_MASK_AND": {
+ "access": "WO",
+ "instances": {
+ "0": "0x08010874"
+ }
+ },
+ "MMIOFIR_MASK_OR": {
+ "access": "WO",
+ "instances": {
+ "0": "0x08010875"
+ }
+ },
"MMIOFIR_ACT0": {
"instances": {
"0": "0x08010876"
@@ -139,6 +163,24 @@
}
}
],
+ "op_rules": {
+ "FIR_SET": {
+ "op_rule": "atomic_or",
+ "reg_name": "MMIOFIR_OR"
+ },
+ "FIR_CLEAR": {
+ "op_rule": "atomic_and",
+ "reg_name": "MMIOFIR_AND"
+ },
+ "MASK_SET": {
+ "op_rule": "atomic_or",
+ "reg_name": "MMIOFIR_MASK_OR"
+ },
+ "MASK_CLEAR": {
+ "op_rule": "atomic_and",
+ "reg_name": "MMIOFIR_MASK_AND"
+ }
+ },
"bits": {
"0": {
"desc": "AFU desc unimp"
diff --git a/chip_data/explorer/node_ocmb_lfir.json b/chip_data/explorer/node_ocmb_lfir.json
index 4786883..2b7d896 100644
--- a/chip_data/explorer/node_ocmb_lfir.json
+++ b/chip_data/explorer/node_ocmb_lfir.json
@@ -7,11 +7,35 @@
"0": "0x0804000A"
}
},
+ "OCMB_LFIR_AND": {
+ "access": "WO",
+ "instances": {
+ "0": "0x0804000B"
+ }
+ },
+ "OCMB_LFIR_OR": {
+ "access": "WO",
+ "instances": {
+ "0": "0x0804000C"
+ }
+ },
"OCMB_LFIR_MASK": {
"instances": {
"0": "0x0804000D"
}
},
+ "OCMB_LFIR_MASK_AND": {
+ "access": "WO",
+ "instances": {
+ "0": "0x0804000E"
+ }
+ },
+ "OCMB_LFIR_MASK_OR": {
+ "access": "WO",
+ "instances": {
+ "0": "0x0804000F"
+ }
+ },
"OCMB_LFIR_ACT0": {
"instances": {
"0": "0x08040010"
@@ -117,6 +141,24 @@
}
}
],
+ "op_rules": {
+ "FIR_SET": {
+ "op_rule": "atomic_or",
+ "reg_name": "OCMB_LFIR_OR"
+ },
+ "FIR_CLEAR": {
+ "op_rule": "atomic_and",
+ "reg_name": "OCMB_LFIR_AND"
+ },
+ "MASK_SET": {
+ "op_rule": "atomic_or",
+ "reg_name": "OCMB_LFIR_MASK_OR"
+ },
+ "MASK_CLEAR": {
+ "op_rule": "atomic_and",
+ "reg_name": "OCMB_LFIR_MASK_AND"
+ }
+ },
"bits": {
"0": {
"desc": "CFIR access PCB error"
diff --git a/chip_data/explorer/node_omi_dl_fir.json b/chip_data/explorer/node_omi_dl_fir.json
index 3b86cbb..0930ea0 100644
--- a/chip_data/explorer/node_omi_dl_fir.json
+++ b/chip_data/explorer/node_omi_dl_fir.json
@@ -7,11 +7,35 @@
"0": "0x08012800"
}
},
+ "OMI_DL_FIR_AND": {
+ "access": "WO",
+ "instances": {
+ "0": "0x08012801"
+ }
+ },
+ "OMI_DL_FIR_OR": {
+ "access": "WO",
+ "instances": {
+ "0": "0x08012802"
+ }
+ },
"OMI_DL_FIR_MASK": {
"instances": {
"0": "0x08012803"
}
},
+ "OMI_DL_FIR_MASK_AND": {
+ "access": "WO",
+ "instances": {
+ "0": "0x08012804"
+ }
+ },
+ "OMI_DL_FIR_MASK_OR": {
+ "access": "WO",
+ "instances": {
+ "0": "0x08012805"
+ }
+ },
"OMI_DL_FIR_ACT0": {
"instances": {
"0": "0x08012806"
@@ -204,6 +228,24 @@
}
}
],
+ "op_rules": {
+ "FIR_SET": {
+ "op_rule": "atomic_or",
+ "reg_name": "OMI_DL_FIR_OR"
+ },
+ "FIR_CLEAR": {
+ "op_rule": "atomic_and",
+ "reg_name": "OMI_DL_FIR_AND"
+ },
+ "MASK_SET": {
+ "op_rule": "atomic_or",
+ "reg_name": "OMI_DL_FIR_MASK_OR"
+ },
+ "MASK_CLEAR": {
+ "op_rule": "atomic_and",
+ "reg_name": "OMI_DL_FIR_MASK_AND"
+ }
+ },
"bits": {
"0": {
"desc": "OMI-DL0 fatal error",
diff --git a/chip_data/explorer/node_rdffir.json b/chip_data/explorer/node_rdffir.json
index eafc663..1abc018 100644
--- a/chip_data/explorer/node_rdffir.json
+++ b/chip_data/explorer/node_rdffir.json
@@ -7,11 +7,35 @@
"0": "0x08011C00"
}
},
+ "RDFFIR_AND": {
+ "access": "WO",
+ "instances": {
+ "0": "0x08011C01"
+ }
+ },
+ "RDFFIR_OR": {
+ "access": "WO",
+ "instances": {
+ "0": "0x08011C02"
+ }
+ },
"RDFFIR_MASK": {
"instances": {
"0": "0x08011C03"
}
},
+ "RDFFIR_MASK_AND": {
+ "access": "WO",
+ "instances": {
+ "0": "0x08011C04"
+ }
+ },
+ "RDFFIR_MASK_OR": {
+ "access": "WO",
+ "instances": {
+ "0": "0x08011C05"
+ }
+ },
"RDFFIR_ACT0": {
"instances": {
"0": "0x08011C06"
@@ -276,6 +300,24 @@
}
}
],
+ "op_rules": {
+ "FIR_SET": {
+ "op_rule": "atomic_or",
+ "reg_name": "RDFFIR_OR"
+ },
+ "FIR_CLEAR": {
+ "op_rule": "atomic_and",
+ "reg_name": "RDFFIR_AND"
+ },
+ "MASK_SET": {
+ "op_rule": "atomic_or",
+ "reg_name": "RDFFIR_MASK_OR"
+ },
+ "MASK_CLEAR": {
+ "op_rule": "atomic_and",
+ "reg_name": "RDFFIR_MASK_AND"
+ }
+ },
"bits": {
"0": {
"desc": "Mainline read MPE on rank 0"
diff --git a/chip_data/explorer/node_srqfir.json b/chip_data/explorer/node_srqfir.json
index c8aa095..64ff720 100644
--- a/chip_data/explorer/node_srqfir.json
+++ b/chip_data/explorer/node_srqfir.json
@@ -7,11 +7,35 @@
"0": "0x08011400"
}
},
+ "SRQFIR_AND": {
+ "access": "WO",
+ "instances": {
+ "0": "0x08011401"
+ }
+ },
+ "SRQFIR_OR": {
+ "access": "WO",
+ "instances": {
+ "0": "0x08011402"
+ }
+ },
"SRQFIR_MASK": {
"instances": {
"0": "0x08011403"
}
},
+ "SRQFIR_MASK_AND": {
+ "access": "WO",
+ "instances": {
+ "0": "0x08011404"
+ }
+ },
+ "SRQFIR_MASK_OR": {
+ "access": "WO",
+ "instances": {
+ "0": "0x08011405"
+ }
+ },
"SRQFIR_ACT0": {
"instances": {
"0": "0x08011406"
@@ -134,6 +158,24 @@
}
}
],
+ "op_rules": {
+ "FIR_SET": {
+ "op_rule": "atomic_or",
+ "reg_name": "SRQFIR_OR"
+ },
+ "FIR_CLEAR": {
+ "op_rule": "atomic_and",
+ "reg_name": "SRQFIR_AND"
+ },
+ "MASK_SET": {
+ "op_rule": "atomic_or",
+ "reg_name": "SRQFIR_MASK_OR"
+ },
+ "MASK_CLEAR": {
+ "op_rule": "atomic_and",
+ "reg_name": "SRQFIR_MASK_AND"
+ }
+ },
"bits": {
"0": {
"desc": "SRQ recoverable error"
diff --git a/chip_data/explorer/node_tlxfir.json b/chip_data/explorer/node_tlxfir.json
index a159694..f6306ac 100644
--- a/chip_data/explorer/node_tlxfir.json
+++ b/chip_data/explorer/node_tlxfir.json
@@ -7,11 +7,35 @@
"0": "0x08012400"
}
},
+ "TLXFIR_AND": {
+ "access": "WO",
+ "instances": {
+ "0": "0x08012401"
+ }
+ },
+ "TLXFIR_OR": {
+ "access": "WO",
+ "instances": {
+ "0": "0x08012402"
+ }
+ },
"TLXFIR_MASK": {
"instances": {
"0": "0x08012403"
}
},
+ "TLXFIR_MASK_AND": {
+ "access": "WO",
+ "instances": {
+ "0": "0x08012404"
+ }
+ },
+ "TLXFIR_MASK_OR": {
+ "access": "WO",
+ "instances": {
+ "0": "0x08012405"
+ }
+ },
"TLXFIR_ACT0": {
"instances": {
"0": "0x08012406"
@@ -159,6 +183,24 @@
}
}
],
+ "op_rules": {
+ "FIR_SET": {
+ "op_rule": "atomic_or",
+ "reg_name": "TLXFIR_OR"
+ },
+ "FIR_CLEAR": {
+ "op_rule": "atomic_and",
+ "reg_name": "TLXFIR_AND"
+ },
+ "MASK_SET": {
+ "op_rule": "atomic_or",
+ "reg_name": "TLXFIR_MASK_OR"
+ },
+ "MASK_CLEAR": {
+ "op_rule": "atomic_and",
+ "reg_name": "TLXFIR_MASK_AND"
+ }
+ },
"bits": {
"0": {
"desc": "Info reg parity error"
diff --git a/chip_data/odyssey/node_cfir_mem.json b/chip_data/odyssey/node_cfir_mem.json
index d87e6b7..fc3fa58 100644
--- a/chip_data/odyssey/node_cfir_mem.json
+++ b/chip_data/odyssey/node_cfir_mem.json
@@ -27,24 +27,72 @@
"0": "0x08040040"
}
},
+ "CFIR_MEM_CHIP_CS_MASK_OR": {
+ "access": "WO",
+ "instances": {
+ "0": "0x08040050"
+ }
+ },
+ "CFIR_MEM_CHIP_CS_MASK_CLEAR": {
+ "access": "WO",
+ "instances": {
+ "0": "0x08040060"
+ }
+ },
"CFIR_MEM_RECOV_MASK": {
"instances": {
"0": "0x08040041"
}
},
+ "CFIR_MEM_RECOV_MASK_OR": {
+ "access": "WO",
+ "instances": {
+ "0": "0x08040051"
+ }
+ },
+ "CFIR_MEM_RECOV_MASK_CLEAR": {
+ "access": "WO",
+ "instances": {
+ "0": "0x08040061"
+ }
+ },
"CFIR_MEM_SP_ATTN_MASK": {
"instances": {
"0": "0x08040042"
}
},
+ "CFIR_MEM_SP_ATTN_MASK_OR": {
+ "access": "WO",
+ "instances": {
+ "0": "0x08040052"
+ }
+ },
+ "CFIR_MEM_SP_ATTN_MASK_CLEAR": {
+ "access": "WO",
+ "instances": {
+ "0": "0x08040062"
+ }
+ },
"CFIR_MEM_UNIT_CS_MASK": {
"instances": {
"0": "0x08040043"
}
+ },
+ "CFIR_MEM_UNIT_CS_MASK_OR": {
+ "access": "WO",
+ "instances": {
+ "0": "0x08040053"
+ }
+ },
+ "CFIR_MEM_UNIT_CS_MASK_CLEAR": {
+ "access": "WO",
+ "instances": {
+ "0": "0x08040063"
+ }
}
},
"isolation_nodes": {
- "CFIR_MEM": {
+ "CFIR_MEM_CHIP_CS": {
"instances": [0],
"rules": [
{
@@ -70,7 +118,102 @@
}
]
}
+ }
+ ],
+ "op_rules": {
+ "MASK_SET": {
+ "op_rule": "atomic_or",
+ "reg_name": "CFIR_MEM_CHIP_CS_MASK_OR"
},
+ "MASK_CLEAR": {
+ "op_rule": "atomic_or",
+ "reg_name": "CFIR_MEM_CHIP_CS_MASK_CLEAR"
+ }
+ },
+ "bits": {
+ "4": {
+ "desc": "Attention from MEM_LOCAL_FIR",
+ "child_node": {
+ "name": "MEM_LOCAL_FIR"
+ }
+ },
+ "5": {
+ "desc": "Attention from DLX_FIR",
+ "child_node": {
+ "name": "DLX_FIR"
+ }
+ },
+ "6": {
+ "desc": "Attention from MCBIST_FIR",
+ "child_node": {
+ "name": "MCBIST_FIR"
+ }
+ },
+ "7": {
+ "desc": "Attention from MMIO_FIR",
+ "child_node": {
+ "name": "MMIO_FIR"
+ }
+ },
+ "8": {
+ "desc": "Attention from RDF_FIR 0",
+ "child_node": {
+ "name": "RDF_FIR",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "9": {
+ "desc": "Attention from RDF_FIR 1",
+ "child_node": {
+ "name": "RDF_FIR",
+ "inst": {
+ "0": 1
+ }
+ }
+ },
+ "10": {
+ "desc": "Attention from SRQ_FIR",
+ "child_node": {
+ "name": "SRQ_FIR"
+ }
+ },
+ "11": {
+ "desc": "Attention from TLX_FIR",
+ "child_node": {
+ "name": "TLX_FIR"
+ }
+ },
+ "12": {
+ "desc": "Attention from ODP_FIR 0",
+ "child_node": {
+ "name": "ODP_FIR",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "13": {
+ "desc": "Attention from ODP_FIR 1",
+ "child_node": {
+ "name": "ODP_FIR",
+ "inst": {
+ "0": 1
+ }
+ }
+ },
+ "14": {
+ "desc": "Attention from OCMB_PHY_FIR",
+ "child_node": {
+ "name": "OCMB_PHY_FIR"
+ }
+ }
+ }
+ },
+ "CFIR_MEM_RECOV": {
+ "instances": [0],
+ "rules": [
{
"attn_type": ["RECOV"],
"node_inst": [0],
@@ -94,7 +237,102 @@
}
]
}
+ }
+ ],
+ "op_rules": {
+ "MASK_SET": {
+ "op_rule": "atomic_or",
+ "reg_name": "CFIR_MEM_RECOV_MASK_OR"
},
+ "MASK_CLEAR": {
+ "op_rule": "atomic_or",
+ "reg_name": "CFIR_MEM_RECOV_MASK_CLEAR"
+ }
+ },
+ "bits": {
+ "4": {
+ "desc": "Attention from MEM_LOCAL_FIR",
+ "child_node": {
+ "name": "MEM_LOCAL_FIR"
+ }
+ },
+ "5": {
+ "desc": "Attention from DLX_FIR",
+ "child_node": {
+ "name": "DLX_FIR"
+ }
+ },
+ "6": {
+ "desc": "Attention from MCBIST_FIR",
+ "child_node": {
+ "name": "MCBIST_FIR"
+ }
+ },
+ "7": {
+ "desc": "Attention from MMIO_FIR",
+ "child_node": {
+ "name": "MMIO_FIR"
+ }
+ },
+ "8": {
+ "desc": "Attention from RDF_FIR 0",
+ "child_node": {
+ "name": "RDF_FIR",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "9": {
+ "desc": "Attention from RDF_FIR 1",
+ "child_node": {
+ "name": "RDF_FIR",
+ "inst": {
+ "0": 1
+ }
+ }
+ },
+ "10": {
+ "desc": "Attention from SRQ_FIR",
+ "child_node": {
+ "name": "SRQ_FIR"
+ }
+ },
+ "11": {
+ "desc": "Attention from TLX_FIR",
+ "child_node": {
+ "name": "TLX_FIR"
+ }
+ },
+ "12": {
+ "desc": "Attention from ODP_FIR 0",
+ "child_node": {
+ "name": "ODP_FIR",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "13": {
+ "desc": "Attention from ODP_FIR 1",
+ "child_node": {
+ "name": "ODP_FIR",
+ "inst": {
+ "0": 1
+ }
+ }
+ },
+ "14": {
+ "desc": "Attention from OCMB_PHY_FIR",
+ "child_node": {
+ "name": "OCMB_PHY_FIR"
+ }
+ }
+ }
+ },
+ "CFIR_MEM_SP_ATTN": {
+ "instances": [0],
+ "rules": [
{
"attn_type": ["SP_ATTN"],
"node_inst": [0],
@@ -118,7 +356,102 @@
}
]
}
+ }
+ ],
+ "op_rules": {
+ "MASK_SET": {
+ "op_rule": "atomic_or",
+ "reg_name": "CFIR_MEM_SP_ATTN_MASK_OR"
},
+ "MASK_CLEAR": {
+ "op_rule": "atomic_or",
+ "reg_name": "CFIR_MEM_SP_ATTN_MASK_CLEAR"
+ }
+ },
+ "bits": {
+ "4": {
+ "desc": "Attention from MEM_LOCAL_FIR",
+ "child_node": {
+ "name": "MEM_LOCAL_FIR"
+ }
+ },
+ "5": {
+ "desc": "Attention from DLX_FIR",
+ "child_node": {
+ "name": "DLX_FIR"
+ }
+ },
+ "6": {
+ "desc": "Attention from MCBIST_FIR",
+ "child_node": {
+ "name": "MCBIST_FIR"
+ }
+ },
+ "7": {
+ "desc": "Attention from MMIO_FIR",
+ "child_node": {
+ "name": "MMIO_FIR"
+ }
+ },
+ "8": {
+ "desc": "Attention from RDF_FIR 0",
+ "child_node": {
+ "name": "RDF_FIR",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "9": {
+ "desc": "Attention from RDF_FIR 1",
+ "child_node": {
+ "name": "RDF_FIR",
+ "inst": {
+ "0": 1
+ }
+ }
+ },
+ "10": {
+ "desc": "Attention from SRQ_FIR",
+ "child_node": {
+ "name": "SRQ_FIR"
+ }
+ },
+ "11": {
+ "desc": "Attention from TLX_FIR",
+ "child_node": {
+ "name": "TLX_FIR"
+ }
+ },
+ "12": {
+ "desc": "Attention from ODP_FIR 0",
+ "child_node": {
+ "name": "ODP_FIR",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "13": {
+ "desc": "Attention from ODP_FIR 1",
+ "child_node": {
+ "name": "ODP_FIR",
+ "inst": {
+ "0": 1
+ }
+ }
+ },
+ "14": {
+ "desc": "Attention from OCMB_PHY_FIR",
+ "child_node": {
+ "name": "OCMB_PHY_FIR"
+ }
+ }
+ }
+ },
+ "CFIR_MEM_UNIT_CS": {
+ "instances": [0],
+ "rules": [
{
"attn_type": ["UNIT_CS"],
"node_inst": [0],
@@ -144,6 +477,16 @@
}
}
],
+ "op_rules": {
+ "MASK_SET": {
+ "op_rule": "atomic_or",
+ "reg_name": "CFIR_MEM_UNIT_CS_MASK_OR"
+ },
+ "MASK_CLEAR": {
+ "op_rule": "atomic_or",
+ "reg_name": "CFIR_MEM_UNIT_CS_MASK_CLEAR"
+ }
+ },
"bits": {
"4": {
"desc": "Attention from MEM_LOCAL_FIR",
diff --git a/chip_data/odyssey/node_cfir_tp.json b/chip_data/odyssey/node_cfir_tp.json
index aabdb6c..4b588e3 100644
--- a/chip_data/odyssey/node_cfir_tp.json
+++ b/chip_data/odyssey/node_cfir_tp.json
@@ -27,24 +27,72 @@
"0": "0x01040040"
}
},
+ "CFIR_TP_CHIP_CS_MASK_OR": {
+ "access": "WO",
+ "instances": {
+ "0": "0x01040050"
+ }
+ },
+ "CFIR_TP_CHIP_CS_MASK_CLEAR": {
+ "access": "WO",
+ "instances": {
+ "0": "0x01040060"
+ }
+ },
"CFIR_TP_RECOV_MASK": {
"instances": {
"0": "0x01040041"
}
},
+ "CFIR_TP_RECOV_MASK_OR": {
+ "access": "WO",
+ "instances": {
+ "0": "0x01040051"
+ }
+ },
+ "CFIR_TP_RECOV_MASK_CLEAR": {
+ "access": "WO",
+ "instances": {
+ "0": "0x01040061"
+ }
+ },
"CFIR_TP_SP_ATTN_MASK": {
"instances": {
"0": "0x01040042"
}
},
+ "CFIR_TP_SP_ATTN_MASK_OR": {
+ "access": "WO",
+ "instances": {
+ "0": "0x01040052"
+ }
+ },
+ "CFIR_TP_SP_ATTN_MASK_CLEAR": {
+ "access": "WO",
+ "instances": {
+ "0": "0x01040062"
+ }
+ },
"CFIR_TP_UNIT_CS_MASK": {
"instances": {
"0": "0x01040043"
}
+ },
+ "CFIR_TP_UNIT_CS_MASK_OR": {
+ "access": "WO",
+ "instances": {
+ "0": "0x01040053"
+ }
+ },
+ "CFIR_TP_UNIT_CS_MASK_CLEAR": {
+ "access": "WO",
+ "instances": {
+ "0": "0x01040063"
+ }
}
},
"isolation_nodes": {
- "CFIR_TP": {
+ "CFIR_TP_CHIP_CS": {
"instances": [0],
"rules": [
{
@@ -70,7 +118,30 @@
}
]
}
+ }
+ ],
+ "op_rules": {
+ "MASK_SET": {
+ "op_rule": "atomic_or",
+ "reg_name": "CFIR_TP_CHIP_CS_MASK_OR"
},
+ "MASK_CLEAR": {
+ "op_rule": "atomic_or",
+ "reg_name": "CFIR_TP_CHIP_CS_MASK_CLEAR"
+ }
+ },
+ "bits": {
+ "4": {
+ "desc": "Attention from TP_LOCAL_FIR",
+ "child_node": {
+ "name": "TP_LOCAL_FIR"
+ }
+ }
+ }
+ },
+ "CFIR_TP_RECOV": {
+ "instances": [0],
+ "rules": [
{
"attn_type": ["RECOV"],
"node_inst": [0],
@@ -94,7 +165,30 @@
}
]
}
+ }
+ ],
+ "op_rules": {
+ "MASK_SET": {
+ "op_rule": "atomic_or",
+ "reg_name": "CFIR_TP_RECOV_MASK_OR"
},
+ "MASK_CLEAR": {
+ "op_rule": "atomic_or",
+ "reg_name": "CFIR_TP_RECOV_MASK_CLEAR"
+ }
+ },
+ "bits": {
+ "4": {
+ "desc": "Attention from TP_LOCAL_FIR",
+ "child_node": {
+ "name": "TP_LOCAL_FIR"
+ }
+ }
+ }
+ },
+ "CFIR_TP_SP_ATTN": {
+ "instances": [0],
+ "rules": [
{
"attn_type": ["SP_ATTN"],
"node_inst": [0],
@@ -118,7 +212,30 @@
}
]
}
+ }
+ ],
+ "op_rules": {
+ "MASK_SET": {
+ "op_rule": "atomic_or",
+ "reg_name": "CFIR_TP_SP_ATTN_MASK_OR"
},
+ "MASK_CLEAR": {
+ "op_rule": "atomic_or",
+ "reg_name": "CFIR_TP_SP_ATTN_MASK_CLEAR"
+ }
+ },
+ "bits": {
+ "4": {
+ "desc": "Attention from TP_LOCAL_FIR",
+ "child_node": {
+ "name": "TP_LOCAL_FIR"
+ }
+ }
+ }
+ },
+ "CFIR_TP_UNIT_CS": {
+ "instances": [0],
+ "rules": [
{
"attn_type": ["UNIT_CS"],
"node_inst": [0],
@@ -144,6 +261,16 @@
}
}
],
+ "op_rules": {
+ "MASK_SET": {
+ "op_rule": "atomic_or",
+ "reg_name": "CFIR_TP_UNIT_CS_MASK_OR"
+ },
+ "MASK_CLEAR": {
+ "op_rule": "atomic_or",
+ "reg_name": "CFIR_TP_UNIT_CS_MASK_CLEAR"
+ }
+ },
"bits": {
"4": {
"desc": "Attention from TP_LOCAL_FIR",
diff --git a/chip_data/odyssey/node_dlx_fir.json b/chip_data/odyssey/node_dlx_fir.json
index c42f877..e687b7f 100644
--- a/chip_data/odyssey/node_dlx_fir.json
+++ b/chip_data/odyssey/node_dlx_fir.json
@@ -7,11 +7,23 @@
"0": "0x08012400"
}
},
+ "DLX_FIR_OR": {
+ "access": "WO",
+ "instances": {
+ "0": "0x08012401"
+ }
+ },
"DLX_FIR_MASK": {
"instances": {
"0": "0x08012402"
}
},
+ "DLX_FIR_MASK_OR": {
+ "access": "WO",
+ "instances": {
+ "0": "0x08012403"
+ }
+ },
"DLX_FIR_CFG_CHIP_CS": {
"instances": {
"0": "0x08012404"
@@ -224,6 +236,24 @@
}
}
],
+ "op_rules": {
+ "FIR_SET": {
+ "op_rule": "atomic_or",
+ "reg_name": "DLX_FIR_OR"
+ },
+ "FIR_CLEAR": {
+ "op_rule": "atomic_or",
+ "reg_name": "DLX_FIR"
+ },
+ "MASK_SET": {
+ "op_rule": "atomic_or",
+ "reg_name": "DLX_FIR_MASK_OR"
+ },
+ "MASK_CLEAR": {
+ "op_rule": "atomic_or",
+ "reg_name": "DLX_FIR_MASK"
+ }
+ },
"bits": {
"0": {
"desc": "Internal parity error in SCOM component"
diff --git a/chip_data/odyssey/node_gfir.json b/chip_data/odyssey/node_gfir.json
index cead761..2312206 100644
--- a/chip_data/odyssey/node_gfir.json
+++ b/chip_data/odyssey/node_gfir.json
@@ -24,7 +24,7 @@
}
},
"isolation_nodes": {
- "GFIR": {
+ "GFIR_CHIP_CS": {
"instances": [0],
"rules": [
{
@@ -34,7 +34,32 @@
"expr_type": "reg",
"reg_name": "GFIR_CHIP_CS"
}
+ }
+ ],
+ "bits": {
+ "1": {
+ "desc": "Attention from TP chiplet",
+ "child_node": {
+ "name": "CFIR_TP_CHIP_CS",
+ "inst": {
+ "0": 0
+ }
+ }
},
+ "8": {
+ "desc": "Attention from MEM chiplet",
+ "child_node": {
+ "name": "CFIR_MEM_CHIP_CS",
+ "inst": {
+ "0": 0
+ }
+ }
+ }
+ }
+ },
+ "GFIR_RECOV": {
+ "instances": [0],
+ "rules": [
{
"attn_type": ["RECOV"],
"node_inst": [0],
@@ -42,7 +67,32 @@
"expr_type": "reg",
"reg_name": "GFIR_RECOV"
}
+ }
+ ],
+ "bits": {
+ "1": {
+ "desc": "Attention from TP chiplet",
+ "child_node": {
+ "name": "CFIR_TP_RECOV",
+ "inst": {
+ "0": 0
+ }
+ }
},
+ "8": {
+ "desc": "Attention from MEM chiplet",
+ "child_node": {
+ "name": "CFIR_MEM_RECOV",
+ "inst": {
+ "0": 0
+ }
+ }
+ }
+ }
+ },
+ "GFIR_SP_ATTN": {
+ "instances": [0],
+ "rules": [
{
"attn_type": ["SP_ATTN"],
"node_inst": [0],
@@ -50,7 +100,32 @@
"expr_type": "reg",
"reg_name": "GFIR_SP_ATTN"
}
+ }
+ ],
+ "bits": {
+ "1": {
+ "desc": "Attention from TP chiplet",
+ "child_node": {
+ "name": "CFIR_TP_SP_ATTN",
+ "inst": {
+ "0": 0
+ }
+ }
},
+ "8": {
+ "desc": "Attention from MEM chiplet",
+ "child_node": {
+ "name": "CFIR_MEM_SP_ATTN",
+ "inst": {
+ "0": 0
+ }
+ }
+ }
+ }
+ },
+ "GFIR_UNIT_CS": {
+ "instances": [0],
+ "rules": [
{
"attn_type": ["UNIT_CS"],
"node_inst": [0],
@@ -64,7 +139,7 @@
"1": {
"desc": "Attention from TP chiplet",
"child_node": {
- "name": "CFIR_TP",
+ "name": "CFIR_TP_UNIT_CS",
"inst": {
"0": 0
}
@@ -73,7 +148,7 @@
"8": {
"desc": "Attention from MEM chiplet",
"child_node": {
- "name": "CFIR_MEM",
+ "name": "CFIR_MEM_UNIT_CS",
"inst": {
"0": 0
}
diff --git a/chip_data/odyssey/node_mcbist_fir.json b/chip_data/odyssey/node_mcbist_fir.json
index cc2f457..f2d2aec 100644
--- a/chip_data/odyssey/node_mcbist_fir.json
+++ b/chip_data/odyssey/node_mcbist_fir.json
@@ -7,11 +7,23 @@
"0": "0x08011400"
}
},
+ "MCBIST_FIR_OR": {
+ "access": "WO",
+ "instances": {
+ "0": "0x08011401"
+ }
+ },
"MCBIST_FIR_MASK": {
"instances": {
"0": "0x08011402"
}
},
+ "MCBIST_FIR_MASK_OR": {
+ "access": "WO",
+ "instances": {
+ "0": "0x08011403"
+ }
+ },
"MCBIST_FIR_CFG_CHIP_CS": {
"instances": {
"0": "0x08011404"
@@ -274,6 +286,24 @@
}
}
],
+ "op_rules": {
+ "FIR_SET": {
+ "op_rule": "atomic_or",
+ "reg_name": "MCBIST_FIR_OR"
+ },
+ "FIR_CLEAR": {
+ "op_rule": "atomic_or",
+ "reg_name": "MCBIST_FIR"
+ },
+ "MASK_SET": {
+ "op_rule": "atomic_or",
+ "reg_name": "MCBIST_FIR_MASK_OR"
+ },
+ "MASK_CLEAR": {
+ "op_rule": "atomic_or",
+ "reg_name": "MCBIST_FIR_MASK"
+ }
+ },
"bits": {
"0": {
"desc": "Internal parity error in scom component"
diff --git a/chip_data/odyssey/node_mem_local_fir.json b/chip_data/odyssey/node_mem_local_fir.json
index b7bc2f0..5f8136e 100644
--- a/chip_data/odyssey/node_mem_local_fir.json
+++ b/chip_data/odyssey/node_mem_local_fir.json
@@ -7,11 +7,23 @@
"0": "0x08040100"
}
},
+ "MEM_LOCAL_FIR_OR": {
+ "access": "WO",
+ "instances": {
+ "0": "0x08040101"
+ }
+ },
"MEM_LOCAL_FIR_MASK": {
"instances": {
"0": "0x08040102"
}
},
+ "MEM_LOCAL_FIR_MASK_OR": {
+ "access": "WO",
+ "instances": {
+ "0": "0x08040103"
+ }
+ },
"MEM_LOCAL_FIR_CFG_CHIP_CS": {
"instances": {
"0": "0x08040104"
@@ -154,6 +166,24 @@
}
}
],
+ "op_rules": {
+ "FIR_SET": {
+ "op_rule": "atomic_or",
+ "reg_name": "MEM_LOCAL_FIR_OR"
+ },
+ "FIR_CLEAR": {
+ "op_rule": "atomic_or",
+ "reg_name": "MEM_LOCAL_FIR"
+ },
+ "MASK_SET": {
+ "op_rule": "atomic_or",
+ "reg_name": "MEM_LOCAL_FIR_MASK_OR"
+ },
+ "MASK_CLEAR": {
+ "op_rule": "atomic_or",
+ "reg_name": "MEM_LOCAL_FIR_MASK"
+ }
+ },
"bits": {
"0": {
"desc": "CFIR/LFIR parity error"
@@ -162,19 +192,59 @@
"desc": "CPLT_CTRL - PCB access error"
},
"2": {
- "desc": "CC - PCB access error"
+ "desc": "CC - PCB access error",
+ "capture_groups": [
+ {
+ "group_name": "MEM_ERR_STATUS_CG",
+ "group_inst": {
+ "0": 0
+ }
+ }
+ ]
},
"3": {
- "desc": "CC - clock control error"
+ "desc": "CC - clock control error",
+ "capture_groups": [
+ {
+ "group_name": "MEM_ERR_STATUS_CG",
+ "group_inst": {
+ "0": 0
+ }
+ }
+ ]
},
"4": {
- "desc": "PSC - PSCOM Access Error"
+ "desc": "PSC - PSCOM Access Error",
+ "capture_groups": [
+ {
+ "group_name": "MEM_PSCOM_STATUS_ERR_CG",
+ "group_inst": {
+ "0": 0
+ }
+ }
+ ]
},
"5": {
- "desc": "PSC - internal or ring interface error"
+ "desc": "PSC - internal or ring interface error",
+ "capture_groups": [
+ {
+ "group_name": "MEM_PSCOM_STATUS_ERR_CG",
+ "group_inst": {
+ "0": 0
+ }
+ }
+ ]
},
"6": {
- "desc": "THERM - various errors"
+ "desc": "THERM - various errors",
+ "capture_groups": [
+ {
+ "group_name": "MEM_DTS_ERR_CG",
+ "group_inst": {
+ "0": 0
+ }
+ }
+ ]
},
"7": {
"desc": "DBG - SCOM parity fail"
@@ -194,31 +264,27 @@
"63": {
"desc": "external local checkstop"
}
- },
- "capture_groups": [
- {
- "group_name": "MEM_LOCAL_FIR",
- "group_inst": {
- "0": 0
- }
- }
- ]
+ }
}
},
"capture_groups": {
- "MEM_LOCAL_FIR": [
- {
- "reg_name": "MEM_PSCOM_STATUS_ERR",
- "reg_inst": {
- "0": 0
- }
- },
+ "MEM_ERR_STATUS_CG": [
{
"reg_name": "MEM_ERR_STATUS",
"reg_inst": {
"0": 0
}
- },
+ }
+ ],
+ "MEM_PSCOM_STATUS_ERR_CG": [
+ {
+ "reg_name": "MEM_PSCOM_STATUS_ERR",
+ "reg_inst": {
+ "0": 0
+ }
+ }
+ ],
+ "MEM_DTS_ERR_CG": [
{
"reg_name": "MEM_DTS_ERR",
"reg_inst": {
diff --git a/chip_data/odyssey/node_mmio_fir.json b/chip_data/odyssey/node_mmio_fir.json
index b2a2de0..8504759 100644
--- a/chip_data/odyssey/node_mmio_fir.json
+++ b/chip_data/odyssey/node_mmio_fir.json
@@ -7,11 +7,23 @@
"0": "0x08010870"
}
},
+ "MMIO_FIR_OR": {
+ "access": "WO",
+ "instances": {
+ "0": "0x08010871"
+ }
+ },
"MMIO_FIR_MASK": {
"instances": {
"0": "0x08010872"
}
},
+ "MMIO_FIR_MASK_OR": {
+ "access": "WO",
+ "instances": {
+ "0": "0x08010873"
+ }
+ },
"MMIO_FIR_CFG_CHIP_CS": {
"instances": {
"0": "0x08010874"
@@ -149,6 +161,24 @@
}
}
],
+ "op_rules": {
+ "FIR_SET": {
+ "op_rule": "atomic_or",
+ "reg_name": "MMIO_FIR_OR"
+ },
+ "FIR_CLEAR": {
+ "op_rule": "atomic_or",
+ "reg_name": "MMIO_FIR"
+ },
+ "MASK_SET": {
+ "op_rule": "atomic_or",
+ "reg_name": "MMIO_FIR_MASK_OR"
+ },
+ "MASK_CLEAR": {
+ "op_rule": "atomic_or",
+ "reg_name": "MMIO_FIR_MASK"
+ }
+ },
"bits": {
"0": {
"desc": "Interal SCOM logic parity error"
diff --git a/chip_data/odyssey/node_ocmb_phy_fir.json b/chip_data/odyssey/node_ocmb_phy_fir.json
index 7a17bdb..f0ef35f 100644
--- a/chip_data/odyssey/node_ocmb_phy_fir.json
+++ b/chip_data/odyssey/node_ocmb_phy_fir.json
@@ -7,11 +7,23 @@
"0": "0x08010C00"
}
},
+ "OCMB_PHY_FIR_OR": {
+ "access": "WO",
+ "instances": {
+ "0": "0x08010C01"
+ }
+ },
"OCMB_PHY_FIR_MASK": {
"instances": {
"0": "0x08010C02"
}
},
+ "OCMB_PHY_FIR_MASK_OR": {
+ "access": "WO",
+ "instances": {
+ "0": "0x08010C03"
+ }
+ },
"OCMB_PHY_FIR_CFG_CHIP_CS": {
"instances": {
"0": "0x08010C04"
@@ -139,6 +151,24 @@
}
}
],
+ "op_rules": {
+ "FIR_SET": {
+ "op_rule": "atomic_or",
+ "reg_name": "OCMB_PHY_FIR_OR"
+ },
+ "FIR_CLEAR": {
+ "op_rule": "atomic_or",
+ "reg_name": "OCMB_PHY_FIR"
+ },
+ "MASK_SET": {
+ "op_rule": "atomic_or",
+ "reg_name": "OCMB_PHY_FIR_MASK_OR"
+ },
+ "MASK_CLEAR": {
+ "op_rule": "atomic_or",
+ "reg_name": "OCMB_PHY_FIR_MASK"
+ }
+ },
"bits": {
"0": {
"desc": "SCOM FSM or FIR register parity error"
diff --git a/chip_data/odyssey/node_odp_fir.json b/chip_data/odyssey/node_odp_fir.json
index efa697e..beb3317 100644
--- a/chip_data/odyssey/node_odp_fir.json
+++ b/chip_data/odyssey/node_odp_fir.json
@@ -8,12 +8,26 @@
"1": "0x08013400"
}
},
+ "ODP_FIR_OR": {
+ "access": "WO",
+ "instances": {
+ "0": "0x08013001",
+ "1": "0x08013401"
+ }
+ },
"ODP_FIR_MASK": {
"instances": {
"0": "0x08013002",
"1": "0x08013402"
}
},
+ "ODP_FIR_MASK_OR": {
+ "access": "WO",
+ "instances": {
+ "0": "0x08013003",
+ "1": "0x08013403"
+ }
+ },
"ODP_FIR_CFG_CHIP_CS": {
"instances": {
"0": "0x08013004",
@@ -433,6 +447,24 @@
}
}
],
+ "op_rules": {
+ "FIR_SET": {
+ "op_rule": "atomic_or",
+ "reg_name": "ODP_FIR_OR"
+ },
+ "FIR_CLEAR": {
+ "op_rule": "atomic_or",
+ "reg_name": "ODP_FIR"
+ },
+ "MASK_SET": {
+ "op_rule": "atomic_or",
+ "reg_name": "ODP_FIR_MASK_OR"
+ },
+ "MASK_CLEAR": {
+ "op_rule": "atomic_or",
+ "reg_name": "ODP_FIR_MASK"
+ }
+ },
"bits": {
"0": {
"desc": "Internal parity error"
diff --git a/chip_data/odyssey/node_rdf_fir.json b/chip_data/odyssey/node_rdf_fir.json
index 3c84186..a90f768 100644
--- a/chip_data/odyssey/node_rdf_fir.json
+++ b/chip_data/odyssey/node_rdf_fir.json
@@ -8,12 +8,26 @@
"1": "0x08012800"
}
},
+ "RDF_FIR_OR": {
+ "access": "WO",
+ "instances": {
+ "0": "0x08011801",
+ "1": "0x08012801"
+ }
+ },
"RDF_FIR_MASK": {
"instances": {
"0": "0x08011802",
"1": "0x08012802"
}
},
+ "RDF_FIR_MASK_OR": {
+ "access": "WO",
+ "instances": {
+ "0": "0x08011803",
+ "1": "0x08012803"
+ }
+ },
"RDF_FIR_CFG_CHIP_CS": {
"instances": {
"0": "0x08011804",
@@ -260,6 +274,24 @@
}
}
],
+ "op_rules": {
+ "FIR_SET": {
+ "op_rule": "atomic_or",
+ "reg_name": "RDF_FIR_OR"
+ },
+ "FIR_CLEAR": {
+ "op_rule": "atomic_or",
+ "reg_name": "RDF_FIR"
+ },
+ "MASK_SET": {
+ "op_rule": "atomic_or",
+ "reg_name": "RDF_FIR_MASK_OR"
+ },
+ "MASK_CLEAR": {
+ "op_rule": "atomic_or",
+ "reg_name": "RDF_FIR_MASK"
+ }
+ },
"bits": {
"0": {
"desc": "Internal SCOM error"
diff --git a/chip_data/odyssey/node_srq_fir.json b/chip_data/odyssey/node_srq_fir.json
index 8989871..24e6b31 100644
--- a/chip_data/odyssey/node_srq_fir.json
+++ b/chip_data/odyssey/node_srq_fir.json
@@ -7,11 +7,23 @@
"0": "0x08011000"
}
},
+ "SRQ_FIR_OR": {
+ "access": "WO",
+ "instances": {
+ "0": "0x08011001"
+ }
+ },
"SRQ_FIR_MASK": {
"instances": {
"0": "0x08011002"
}
},
+ "SRQ_FIR_MASK_OR": {
+ "access": "WO",
+ "instances": {
+ "0": "0x08011003"
+ }
+ },
"SRQ_FIR_CFG_CHIP_CS": {
"instances": {
"0": "0x08011004"
@@ -174,6 +186,24 @@
}
}
],
+ "op_rules": {
+ "FIR_SET": {
+ "op_rule": "atomic_or",
+ "reg_name": "SRQ_FIR_OR"
+ },
+ "FIR_CLEAR": {
+ "op_rule": "atomic_or",
+ "reg_name": "SRQ_FIR"
+ },
+ "MASK_SET": {
+ "op_rule": "atomic_or",
+ "reg_name": "SRQ_FIR_MASK_OR"
+ },
+ "MASK_CLEAR": {
+ "op_rule": "atomic_or",
+ "reg_name": "SRQ_FIR_MASK"
+ }
+ },
"bits": {
"0": {
"desc": "Internal parity error"
@@ -313,7 +343,10 @@
"45": {
"desc": "DSM errors port1"
},
- "46:48": {
+ "46": {
+ "desc": "Firmware initiated channel fail"
+ },
+ "47:48": {
"desc": "reserved"
}
},
diff --git a/chip_data/odyssey/node_tlx_fir.json b/chip_data/odyssey/node_tlx_fir.json
index a9fde05..7ae6bc8 100644
--- a/chip_data/odyssey/node_tlx_fir.json
+++ b/chip_data/odyssey/node_tlx_fir.json
@@ -7,11 +7,23 @@
"0": "0x08012000"
}
},
+ "TLX_FIR_OR": {
+ "access": "WO",
+ "instances": {
+ "0": "0x08012001"
+ }
+ },
"TLX_FIR_MASK": {
"instances": {
"0": "0x08012002"
}
},
+ "TLX_FIR_MASK_OR": {
+ "access": "WO",
+ "instances": {
+ "0": "0x08012003"
+ }
+ },
"TLX_FIR_CFG_CHIP_CS": {
"instances": {
"0": "0x08012004"
@@ -179,6 +191,24 @@
}
}
],
+ "op_rules": {
+ "FIR_SET": {
+ "op_rule": "atomic_or",
+ "reg_name": "TLX_FIR_OR"
+ },
+ "FIR_CLEAR": {
+ "op_rule": "atomic_or",
+ "reg_name": "TLX_FIR"
+ },
+ "MASK_SET": {
+ "op_rule": "atomic_or",
+ "reg_name": "TLX_FIR_MASK_OR"
+ },
+ "MASK_CLEAR": {
+ "op_rule": "atomic_or",
+ "reg_name": "TLX_FIR_MASK"
+ }
+ },
"bits": {
"0": {
"desc": "Internal parity error"
diff --git a/chip_data/odyssey/node_tp_local_fir.json b/chip_data/odyssey/node_tp_local_fir.json
index a0b98e2..be54371 100644
--- a/chip_data/odyssey/node_tp_local_fir.json
+++ b/chip_data/odyssey/node_tp_local_fir.json
@@ -7,11 +7,23 @@
"0": "0x01040100"
}
},
+ "TP_LOCAL_FIR_OR": {
+ "access": "WO",
+ "instances": {
+ "0": "0x01040101"
+ }
+ },
"TP_LOCAL_FIR_MASK": {
"instances": {
"0": "0x01040102"
}
},
+ "TP_LOCAL_FIR_MASK_OR": {
+ "access": "WO",
+ "instances": {
+ "0": "0x01040103"
+ }
+ },
"TP_LOCAL_FIR_CFG_CHIP_CS": {
"instances": {
"0": "0x01040104"
@@ -121,6 +133,16 @@
"instances": {
"0": "0x000D001B"
}
+ },
+ "SPICTL0_ERROR_INJECT": {
+ "instances": {
+ "0": "0x00070000"
+ }
+ },
+ "SPICTL0_STATUS_REG": {
+ "instances": {
+ "0": "0x00070008"
+ }
}
},
"isolation_nodes": {
@@ -224,6 +246,24 @@
}
}
],
+ "op_rules": {
+ "FIR_SET": {
+ "op_rule": "atomic_or",
+ "reg_name": "TP_LOCAL_FIR_OR"
+ },
+ "FIR_CLEAR": {
+ "op_rule": "atomic_or",
+ "reg_name": "TP_LOCAL_FIR"
+ },
+ "MASK_SET": {
+ "op_rule": "atomic_or",
+ "reg_name": "TP_LOCAL_FIR_MASK_OR"
+ },
+ "MASK_CLEAR": {
+ "op_rule": "atomic_or",
+ "reg_name": "TP_LOCAL_FIR_MASK"
+ }
+ },
"bits": {
"0": {
"desc": "CFIR/LFIR parity error"
@@ -232,19 +272,59 @@
"desc": "CPLT_CTRL - PCB access error"
},
"2": {
- "desc": "CC - PCB access error"
+ "desc": "CC - PCB access error",
+ "capture_groups": [
+ {
+ "group_name": "TP_ERR_STATUS_CG",
+ "group_inst": {
+ "0": 0
+ }
+ }
+ ]
},
"3": {
- "desc": "CC - clock control error"
+ "desc": "CC - clock control error",
+ "capture_groups": [
+ {
+ "group_name": "TP_ERR_STATUS_CG",
+ "group_inst": {
+ "0": 0
+ }
+ }
+ ]
},
"4": {
- "desc": "PSC - PSCOM Access Error"
+ "desc": "PSC - PSCOM Access Error",
+ "capture_groups": [
+ {
+ "group_name": "TP_PSCOM_STATUS_ERR_CG",
+ "group_inst": {
+ "0": 0
+ }
+ }
+ ]
},
"5": {
- "desc": "PSC - internal or ring interface error"
+ "desc": "PSC - internal or ring interface error",
+ "capture_groups": [
+ {
+ "group_name": "TP_PSCOM_STATUS_ERR_CG",
+ "group_inst": {
+ "0": 0
+ }
+ }
+ ]
},
"6": {
- "desc": "THERM - various errors"
+ "desc": "THERM - various errors",
+ "capture_groups": [
+ {
+ "group_name": "TP_DTS_ERR_CG",
+ "group_inst": {
+ "0": 0
+ }
+ }
+ ]
},
"7": {
"desc": "DBG - SCOM parity fail"
@@ -259,16 +339,40 @@
"desc": "Trace00 - SCOM parity error"
},
"11": {
- "desc": "ITR - FMU error"
+ "desc": "ITR - FMU error",
+ "capture_groups": [
+ {
+ "group_name": "TP_FMU_ERR_RPT_CG",
+ "group_inst": {
+ "0": 0
+ }
+ }
+ ]
},
"12": {
"desc": "ITR - PCB error"
},
"13": {
- "desc": "PCB master - timeout"
+ "desc": "PCB master - timeout",
+ "capture_groups": [
+ {
+ "group_name": "PCBCTL_ERR_CG",
+ "group_inst": {
+ "0": 0
+ }
+ }
+ ]
},
"14": {
- "desc": "I2CM - parity errors"
+ "desc": "I2CM - parity errors",
+ "capture_groups": [
+ {
+ "group_name": "RESET_REG_B_CG",
+ "group_inst": {
+ "0": 0
+ }
+ }
+ ]
},
"15:17": {
"desc": "unused"
@@ -323,25 +427,65 @@
"desc": "unused"
},
"30": {
- "desc": "PCB controller - multicast group member count underrun"
+ "desc": "PCB controller - multicast group member count underrun",
+ "capture_groups": [
+ {
+ "group_name": "PCBCTL_ERR_CG",
+ "group_inst": {
+ "0": 0
+ }
+ }
+ ]
},
"31": {
- "desc": "PCB controller - parity error"
+ "desc": "PCB controller - parity error",
+ "capture_groups": [
+ {
+ "group_name": "PCBCTL_ERR_CG",
+ "group_inst": {
+ "0": 0
+ }
+ }
+ ]
},
"32:35": {
"desc": "unused"
},
"36": {
- "desc": "PIB interface - RAM UE ECC error"
+ "desc": "PIB interface - RAM UE ECC error",
+ "capture_groups": [
+ {
+ "group_name": "PPE_PIBMEM_STATUS_REG_CG",
+ "group_inst": {
+ "0": 0
+ }
+ }
+ ]
},
"37": {
- "desc": "Direct interface to PIBMEM - RAM UE ECC error"
+ "desc": "Direct interface to PIBMEM - RAM UE ECC error",
+ "capture_groups": [
+ {
+ "group_name": "PPE_PIBMEM_STATUS_REG_CG",
+ "group_inst": {
+ "0": 0
+ }
+ }
+ ]
},
"38:44": {
"desc": "unused"
},
"45": {
- "desc": "SPI controller 0 error"
+ "desc": "SPI controller 0 error",
+ "capture_groups": [
+ {
+ "group_name": "SPI_CONTROLLER",
+ "group_inst": {
+ "0": 0
+ }
+ }
+ ]
},
"46:62": {
"desc": "unused"
@@ -349,49 +493,51 @@
"63": {
"desc": "external local checkstop"
}
- },
- "capture_groups": [
- {
- "group_name": "TP_LOCAL_FIR",
- "group_inst": {
- "0": 0
- }
- }
- ]
+ }
}
},
"capture_groups": {
- "TP_LOCAL_FIR": [
- {
- "reg_name": "TP_ERR_STATUS",
- "reg_inst": {
- "0": 0
- }
- },
- {
- "reg_name": "TP_PSCOM_STATUS_ERR",
- "reg_inst": {
- "0": 0
- }
- },
- {
- "reg_name": "TP_DTS_ERR",
- "reg_inst": {
- "0": 0
- }
- },
- {
- "reg_name": "TP_FMU_ERR_RPT",
- "reg_inst": {
- "0": 0
- }
- },
+ "PCBCTL_ERR_CG": [
{
"reg_name": "PCBCTL_ERR",
"reg_inst": {
"0": 0
}
- },
+ }
+ ],
+ "TP_FMU_ERR_RPT_CG": [
+ {
+ "reg_name": "TP_FMU_ERR_RPT",
+ "reg_inst": {
+ "0": 0
+ }
+ }
+ ],
+ "TP_DTS_ERR_CG": [
+ {
+ "reg_name": "TP_DTS_ERR",
+ "reg_inst": {
+ "0": 0
+ }
+ }
+ ],
+ "TP_PSCOM_STATUS_ERR_CG": [
+ {
+ "reg_name": "TP_PSCOM_STATUS_ERR",
+ "reg_inst": {
+ "0": 0
+ }
+ }
+ ],
+ "TP_ERR_STATUS_CG": [
+ {
+ "reg_name": "TP_ERR_STATUS",
+ "reg_inst": {
+ "0": 0
+ }
+ }
+ ],
+ "RESET_REG_B_CG": [
{
"reg_name": "RESET_REG_B",
"reg_inst": {
@@ -399,6 +545,28 @@
}
}
],
+ "SPI_CONTROLLER": [
+ {
+ "reg_name": "SPICTL0_ERROR_INJECT",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "SPICTL0_STATUS_REG",
+ "reg_inst": {
+ "0": 0
+ }
+ }
+ ],
+ "PPE_PIBMEM_STATUS_REG_CG": [
+ {
+ "reg_name": "PPE_PIBMEM_STATUS_REG",
+ "reg_inst": {
+ "0": 0
+ }
+ }
+ ],
"SPPE_HW_ERROR": [
{
"reg_name": "PPE_XIRAMDBG",
diff --git a/chip_data/p10_10/node_lpc_fir.json b/chip_data/p10_10/node_lpc_fir.json
index eaf3526..649e9be 100644
--- a/chip_data/p10_10/node_lpc_fir.json
+++ b/chip_data/p10_10/node_lpc_fir.json
@@ -100,28 +100,28 @@
],
"bits": {
"0": {
- "desc": "OPB_Master_LS_received_a_transfer_size_value_unequal_to_1-_or_2-_or_4-Byte"
+ "desc": "OPB Master LS received transfer size unequal to 1- or 2- or 4-Byte"
},
"1": {
- "desc": "OPB_Master_LS_received_a_invalid_command_no_ci_store_and_no_ci_load"
+ "desc": "OPB Master LS received an action 0 invalid command no ci store and no ci load"
},
"2": {
- "desc": "OPB_Master_LS_received_a_address_which_was_not_aligned_to_the_received_transfer_size"
+ "desc": "OPB Master LS received a address not aligned to received transfer size"
},
"3": {
- "desc": "OPB_Master_LS_detected_OPB_ErrAck_which_was_activated_by_the_accessed_OPB_slave"
+ "desc": "OPB Master LS detected OPB ErrAck activated by the accessed OPB slave"
},
"4": {
- "desc": "the_OPB_arbiter_activated_the_OPB_Timeout_signal_Typical_reason_is_that_the_OPB_access_did_not_hit_any_available_OPB_slave"
+ "desc": "The OPB arbiter activated OPB Timeout signal"
},
"5": {
- "desc": "the_OPB_Master_LS_was_not_able_to_end_the_requested_OPB_access_within_the_OPB_Master_LS_hang_timeout_time"
+ "desc": "OPB Master LS not able to end requested OPB access within the OPB Master LS hang timeout time"
},
"6": {
- "desc": "a parity_error_was_detected_in_the_OPB_Master_LS_command_buffer"
+ "desc": "A parity error was detected in the OPB Master LS command buffer"
},
"7": {
- "desc": "a parity_error_was_detected_in_the_OPB_Master_LS_data_buffer"
+ "desc": "A parity error was detected in the OPB Master LS data buffer"
},
"8": {
"desc": "spare"
diff --git a/chip_data/p10_10/node_mcd_fir.json b/chip_data/p10_10/node_mcd_fir.json
index a257c03..ad3d1c7 100644
--- a/chip_data/p10_10/node_mcd_fir.json
+++ b/chip_data/p10_10/node_mcd_fir.json
@@ -131,10 +131,10 @@
],
"bits": {
"0": {
- "desc": "MCD array ECC correctable error"
+ "desc": "MCD array ECC uncorrectable error"
},
"1": {
- "desc": "MCD array ECC uncorrectable error"
+ "desc": "MCD array ECC correctable error"
},
"2": {
"desc": "MCD PowerBus address parity error"
diff --git a/chip_data/p10_10/node_vas_fir.json b/chip_data/p10_10/node_vas_fir.json
index 63fa056..22ab75e 100644
--- a/chip_data/p10_10/node_vas_fir.json
+++ b/chip_data/p10_10/node_vas_fir.json
@@ -167,10 +167,10 @@
"desc": "Correctable ECC error detected in RG logic"
},
"13": {
- "desc": "ECC Correctable Error detected on CQ outbound PowerBus interface"
+ "desc": "ECC Correctable Error detected on CQ outbound PB interface"
},
"14": {
- "desc": "ECC Uncorrectable Error detected on CQ outbound PowerBus interface"
+ "desc": "ECC Uncorrectable Error detected on CQ outbound PB interface"
},
"15": {
"desc": "PowerBus state machine hang detected in CQ logic"
diff --git a/chip_data/p10_20/node_lpc_fir.json b/chip_data/p10_20/node_lpc_fir.json
index 38785ec..06f702f 100644
--- a/chip_data/p10_20/node_lpc_fir.json
+++ b/chip_data/p10_20/node_lpc_fir.json
@@ -100,28 +100,28 @@
],
"bits": {
"0": {
- "desc": "OPB_Master_LS_received_a_transfer_size_value_unequal_to_1-_or_2-_or_4-Byte"
+ "desc": "OPB Master LS received transfer size unequal to 1- or 2- or 4-Byte"
},
"1": {
- "desc": "OPB_Master_LS_received_a_invalid_command_no_ci_store_and_no_ci_load"
+ "desc": "OPB Master LS received an action 0 invalid command no ci store and no ci load"
},
"2": {
- "desc": "OPB_Master_LS_received_a_address_which_was_not_aligned_to_the_received_transfer_size"
+ "desc": "OPB Master LS received a address not aligned to received transfer size"
},
"3": {
- "desc": "OPB_Master_LS_detected_OPB_ErrAck_which_was_activated_by_the_accessed_OPB_slave"
+ "desc": "OPB Master LS detected OPB ErrAck activated by the accessed OPB slave"
},
"4": {
- "desc": "the_OPB_arbiter_activated_the_OPB_Timeout_signal_Typical_reason_is_that_the_OPB_access_did_not_hit_any_available_OPB_slave"
+ "desc": "The OPB arbiter activated OPB Timeout signal"
},
"5": {
- "desc": "the_OPB_Master_LS_was_not_able_to_end_the_requested_OPB_access_within_the_OPB_Master_LS_hang_timeout_time"
+ "desc": "OPB Master LS not able to end requested OPB access within the OPB Master LS hang timeout time"
},
"6": {
- "desc": "a parity_error_was_detected_in_the_OPB_Master_LS_command_buffer"
+ "desc": "A parity error was detected in the OPB Master LS command buffer"
},
"7": {
- "desc": "a parity_error_was_detected_in_the_OPB_Master_LS_data_buffer"
+ "desc": "A parity error was detected in the OPB Master LS data buffer"
},
"8": {
"desc": "spare"
diff --git a/chip_data/p10_20/node_mcd_fir.json b/chip_data/p10_20/node_mcd_fir.json
index 6bd3572..e929004 100644
--- a/chip_data/p10_20/node_mcd_fir.json
+++ b/chip_data/p10_20/node_mcd_fir.json
@@ -131,10 +131,10 @@
],
"bits": {
"0": {
- "desc": "MCD array ECC correctable error"
+ "desc": "MCD array ECC uncorrectable error"
},
"1": {
- "desc": "MCD array ECC uncorrectable error"
+ "desc": "MCD array ECC correctable error"
},
"2": {
"desc": "MCD PowerBus address parity error"
diff --git a/chip_data/p10_20/node_vas_fir.json b/chip_data/p10_20/node_vas_fir.json
index fdfb485..e366cd9 100644
--- a/chip_data/p10_20/node_vas_fir.json
+++ b/chip_data/p10_20/node_vas_fir.json
@@ -167,10 +167,10 @@
"desc": "Correctable ECC error detected in RG logic"
},
"13": {
- "desc": "ECC Correctable Error detected on CQ outbound PowerBus interface"
+ "desc": "ECC Correctable Error detected on CQ outbound PB interface"
},
"14": {
- "desc": "ECC Uncorrectable Error detected on CQ outbound PowerBus interface"
+ "desc": "ECC Uncorrectable Error detected on CQ outbound PB interface"
},
"15": {
"desc": "PowerBus state machine hang detected in CQ logic"
diff --git a/chip_data/pyprd/chip_data/binary.py b/chip_data/pyprd/chip_data/binary.py
index a812171..cbd281d 100644
--- a/chip_data/pyprd/chip_data/binary.py
+++ b/chip_data/pyprd/chip_data/binary.py
@@ -90,6 +90,14 @@
return _num(1, iterable)
+def _op_name(name: str) -> bytes:
+ return _hash(1, name)
+
+
+def _num_op_rules(iterable: iter) -> bytes:
+ return _num(1, iterable)
+
+
# -----------------------------------------------------------------------------
# Isolation node capture register support
@@ -243,7 +251,7 @@
# Header information.
data += "CHIPDATA".encode()
data += _model_ec(supported_model_ec[model_ec].id)
- data += _version(2)
+ data += _version(3)
# Register information.
data += "REGS".encode()
@@ -268,6 +276,12 @@
data += _reg_type(iso_node.reg_type)
data += _num_inst(iso_node.instances)
+ data += _num_op_rules(iso_node.op_rules)
+ for op_name, op_rule in sorted(iso_node.op_rules.items()):
+ data += _op_name(op_name)
+ data += _op_name(op_rule.op_rule)
+ data += _reg_name(op_rule.reg_name)
+
for node_inst in sorted(iso_node.instances):
cap_regs = _cap_regs(
node_inst,
diff --git a/chip_data/pyprd/chip_data/chip_data.py b/chip_data/pyprd/chip_data/chip_data.py
index 34663d4..8640dd3 100644
--- a/chip_data/pyprd/chip_data/chip_data.py
+++ b/chip_data/pyprd/chip_data/chip_data.py
@@ -210,6 +210,29 @@
self.capture_groups.append(group)
+def _check_op_type(op_type: str) -> str:
+ supported = ["FIR_SET", "FIR_CLEAR", "MASK_SET", "MASK_CLEAR"]
+ assert op_type in supported, "Unsupported operation type: " + op_type
+ return op_type
+
+
+def _check_op_rule(op_rule: str) -> str:
+ supported = [
+ "atomic_or",
+ "atomic_and",
+ "read_set_write",
+ "read_clear_write",
+ ]
+ assert op_rule in supported, "Unsupported operation rule: " + op_rule
+ return op_rule
+
+
+class IsolationWriteOps:
+ def __init__(self, op_rule: str, reg_name: str):
+ self.op_rule = _check_op_rule(op_rule)
+ self.reg_name = reg_name
+
+
class IsolationNode:
def __init__(self, reg_type: str = "SCOM"):
self.reg_type = _check_reg_type(reg_type)
@@ -217,6 +240,7 @@
self.rules = []
self.bits = {}
self.capture_groups = []
+ self.op_rules = {}
def addRule(self, rule: IsolationRule):
self.rules.append(rule)
@@ -239,6 +263,9 @@
def addCaptureGroup(self, group: CaptureGroup):
self.capture_groups.append(group)
+ def addWriteOp(self, op_type: str, op_rule: IsolationWriteOps):
+ self.op_rules[_check_op_type(op_type)] = op_rule
+
class RootNode:
def __init__(self, name: str, inst: int):
diff --git a/chip_data/pyprd/chip_data/json.py b/chip_data/pyprd/chip_data/json.py
index 67a3e06..e445736 100644
--- a/chip_data/pyprd/chip_data/json.py
+++ b/chip_data/pyprd/chip_data/json.py
@@ -76,6 +76,8 @@
j["instances"] = o.instances
j["rules"] = o.rules
+ if o.op_rules:
+ j["op_rules"] = o.op_rules
j["bits"] = o.bits
if o.capture_groups:
@@ -153,6 +155,10 @@
return j
+ if isinstance(o, cd.IsolationWriteOps):
+ j = {"op_rule": o.op_rule, "reg_name": o.reg_name}
+ return j
+
if isinstance(o, cd.RootNode):
return {
"name": o.name,
@@ -270,6 +276,10 @@
return bit
+def _decodeWriteOp(d: dict) -> cd.IsolationWriteOps:
+ return cd.IsolationWriteOps(d["op_rule"], d["reg_name"])
+
+
def _decodeIsolationNode(d: dict) -> cd.IsolationNode:
reg_type = d["reg_type"] if "reg_type" in d else "SCOM"
@@ -288,6 +298,10 @@
for e in d["capture_groups"]:
node.addCaptureGroup(_decodeCaptureGroup(e))
+ if "op_rules" in d:
+ for k, v in d["op_rules"].items():
+ node.addWriteOp(k, _decodeWriteOp(v))
+
return node
diff --git a/chip_data/schema/chip-data-schema-v01.json b/chip_data/schema/chip-data-schema-v01.json
index d43b248..ff4decf 100644
--- a/chip_data/schema/chip-data-schema-v01.json
+++ b/chip_data/schema/chip-data-schema-v01.json
@@ -137,6 +137,15 @@
}
}
},
+ "op_rules": {
+ "type": "object",
+ "additionalProperties": false,
+ "patternProperties": {
+ "^\\w+$": {
+ "$ref": "#/$defs/isolation_op_rules"
+ }
+ }
+ },
"capture_groups": {
"type": "array",
"minItems": 1,
@@ -299,6 +308,23 @@
}
}
},
+ "isolation_op_rules": {
+ "type": "object",
+ "required": ["op_rule", "reg_name"],
+ "additionalProperties": false,
+ "properties": {
+ "op_rule": {
+ "type": "string",
+ "enum": [
+ "atomic_or",
+ "atomic_and",
+ "read_set_write",
+ "read_clear_write"
+ ]
+ },
+ "reg_name": { "#ref": "#/$defs/name" }
+ }
+ },
"capture_group": {
"type": "object",
"required": ["group_name", "group_inst"],