Copied Chip Data XML from Hostboot project
Signed-off-by: Zane Shelley <zshelle@us.ibm.com>
Change-Id: I0a230be8ba2840768e2097fd4e479c8feb8fc452
diff --git a/xml/p10/node_mc_misc_fir.xml b/xml/p10/node_mc_misc_fir.xml
new file mode 100644
index 0000000..78681c5
--- /dev/null
+++ b/xml/p10/node_mc_misc_fir.xml
@@ -0,0 +1,26 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10" name="MC_MISC_FIR" reg_type="SCOM">
+ <local_fir config="W2" name="MC_MISC_FIR">
+ <instance addr="0x0C010F00" reg_inst="0"/>
+ <instance addr="0x0D010F00" reg_inst="1"/>
+ <instance addr="0x0E010F00" reg_inst="2"/>
+ <instance addr="0x0F010F00" reg_inst="3"/>
+ <action attn_type="CS" config="000"/>
+ <action attn_type="RE" config="010"/>
+ <action attn_type="SPA" config="100"/>
+ <action attn_type="UCS" config="110"/>
+ <action attn_type="HA" config="001"/>
+ </local_fir>
+ <bit pos="0">WAT Debug Bus Attention. This is a way for the WAT debug bus to trigger an attention.</bit>
+ <bit pos="1">SCOM DBGSRC Register parity Error. Indicates that control register for Debug logic has taken a parity error.</bit>
+ <bit pos="2">SCOM Recoverable Register Parity Error. This bit is set when a recoverable parity error on SCOM registers AACR or MCDBG_SCOM_CFG takes place. These register errors are config-related, unable to corrupt data or mainline.</bit>
+ <bit pos="3">Spare fir; hooked up to the parity error dectect of the SPARE scom register</bit>
+ <bit pos="4">Indicates that an application interrupt was received from the OCMB on</bit>
+ <bit pos="5">Indicates that an application interrupt was received from the OCMB on</bit>
+ <bit pos="6">Indicates that an application interrupt was received from the OCMB on</bit>
+ <bit pos="7">Indicates that an application interrupt was received from the OCMB on</bit>
+ <bit pos="8">Parity Error taken on MCEBUSEN[0,1,2,3] regs.</bit>
+ <bit pos="9">Parity Error taken on WAT* Regs.</bit>
+ <bit pos="10">Reserved Fir Bit 10.</bit>
+ <bit pos="11">Reserved Fir Bit 11.</bit>
+</attn_node>