xml/p10/node_mc_fir_p10_10.xml

<?xml version="1.0" encoding="UTF-8"?>
<attn_node model_ec="P10_10" name="MC_FIR" reg_type="SCOM">
    <local_fir config="W2" name="MC_FIR">
        <instance addr="0x0C010C00" reg_inst="0"/>
        <instance addr="0x0D010C00" reg_inst="1"/>
        <instance addr="0x0E010C00" reg_inst="2"/>
        <instance addr="0x0F010C00" reg_inst="3"/>
        <action attn_type="CS" config="000"/>
        <action attn_type="RE" config="010"/>
        <action attn_type="SPA" config="100"/>
        <action attn_type="UCS" config="110"/>
        <action attn_type="HA" config="001"/>
    </local_fir>
    <bit pos="0">If '1', a MC recoverable error was detected.  See the MCERPTx register description for a list of errors that cause this FIR to be set.</bit>
    <bit pos="1">If 1, a MC non-recoverable error was detected.  See the MCERPTx register description for a list of errors that cause this FIR to be set.</bit>
    <bit pos="2">If '1', an PowerBus protocol error was detected. (for example, a HPC_WR is snooped when a HPC_WR to the same address is active).</bit>
    <bit pos="3">If '1', a command was issued to inband address space using a</bit>
    <bit pos="4">If '1', an address match on more that one Memory BAR was detected.</bit>
    <bit pos="5">If set, the ECC syndrome for PowerBus write data is non-zero (for chan0/1 in pbi01, chann2/3 in pbi23)</bit>
    <bit pos="6">Reserved[6].</bit>
    <bit pos="7">Reserved[7].</bit>
    <bit pos="8">If '1', a command list state machine has timed out.</bit>
    <bit pos="9">Reserved[9].</bit>
    <bit pos="10">Reserved[10].</bit>
    <bit pos="11">If '1', a MCS WAT0 event has occurred.</bit>
    <bit pos="12">If '1', a MCS WAT1 event has occurred.</bit>
    <bit pos="13">If '1', a MCS WAT2 event has occurred.</bit>
    <bit pos="14">If '1', a MCS WAT3 event has occurred.</bit>
    <bit pos="15">Plus One Prefetch generated command did not hit any BARs</bit>
    <bit pos="16">Plus One Prefetch generated command hit config or mmio BAR</bit>
    <bit pos="17">Parity Error in WAT/Debug config register.</bit>
    <bit pos="18">Reserved[18].</bit>
    <bit pos="19">Reserved[19].</bit>
    <bit pos="20">Incoming Powerbus Command hit multiple valid configured topology IDs</bit>
    <bit pos="21">Reserved[21].</bit>
    <bit pos="22">Access to secure memory facility failed. Improper access privilege by originating thread.</bit>
    <bit pos="23">Caused by multiple sync commands being received by an MC at a time, or while one is pending</bit>
</attn_node>