xml/p10/node_eq_qme_fir.xml

<?xml version="1.0" encoding="UTF-8"?>
<attn_node model_ec="P10_20" name="EQ_QME_FIR" reg_type="SCOM">
    <register name="EQ_QME_FIR">
        <instance addr="0x200E0000" reg_inst="0"/>
        <instance addr="0x210E0000" reg_inst="1"/>
        <instance addr="0x220E0000" reg_inst="2"/>
        <instance addr="0x230E0000" reg_inst="3"/>
        <instance addr="0x240E0000" reg_inst="4"/>
        <instance addr="0x250E0000" reg_inst="5"/>
        <instance addr="0x260E0000" reg_inst="6"/>
        <instance addr="0x270E0000" reg_inst="7"/>
    </register>
    <register name="EQ_QME_FIR_MASK">
        <instance addr="0x200E0004" reg_inst="0"/>
        <instance addr="0x210E0004" reg_inst="1"/>
        <instance addr="0x220E0004" reg_inst="2"/>
        <instance addr="0x230E0004" reg_inst="3"/>
        <instance addr="0x240E0004" reg_inst="4"/>
        <instance addr="0x250E0004" reg_inst="5"/>
        <instance addr="0x260E0004" reg_inst="6"/>
        <instance addr="0x270E0004" reg_inst="7"/>
    </register>
    <register name="EQ_QME_FIR_ACT0">
        <instance addr="0x200E0008" reg_inst="0"/>
        <instance addr="0x210E0008" reg_inst="1"/>
        <instance addr="0x220E0008" reg_inst="2"/>
        <instance addr="0x230E0008" reg_inst="3"/>
        <instance addr="0x240E0008" reg_inst="4"/>
        <instance addr="0x250E0008" reg_inst="5"/>
        <instance addr="0x260E0008" reg_inst="6"/>
        <instance addr="0x270E0008" reg_inst="7"/>
    </register>
    <register name="EQ_QME_FIR_ACT1">
        <instance addr="0x200E000c" reg_inst="0"/>
        <instance addr="0x210E000c" reg_inst="1"/>
        <instance addr="0x220E000c" reg_inst="2"/>
        <instance addr="0x230E000c" reg_inst="3"/>
        <instance addr="0x240E000c" reg_inst="4"/>
        <instance addr="0x250E000c" reg_inst="5"/>
        <instance addr="0x260E000c" reg_inst="6"/>
        <instance addr="0x270E000c" reg_inst="7"/>
    </register>
    <rule attn_type="CS" node_inst="0:7">
        <!-- FIR & ~MASK & ~ACT0 & ~ACT1 -->
        <expr type="and">
            <expr type="reg" value1="EQ_QME_FIR"/>
            <expr type="not">
                <expr type="reg" value1="EQ_QME_FIR_MASK"/>
            </expr>
            <expr type="not">
                <expr type="reg" value1="EQ_QME_FIR_ACT0"/>
            </expr>
            <expr type="not">
                <expr type="reg" value1="EQ_QME_FIR_ACT1"/>
            </expr>
        </expr>
    </rule>
    <rule attn_type="RE" node_inst="0:7">
        <!-- FIR & ~MASK & ~ACT0 & ACT1 -->
        <expr type="and">
            <expr type="reg" value1="EQ_QME_FIR"/>
            <expr type="not">
                <expr type="reg" value1="EQ_QME_FIR_MASK"/>
            </expr>
            <expr type="not">
                <expr type="reg" value1="EQ_QME_FIR_ACT0"/>
            </expr>
            <expr type="reg" value1="EQ_QME_FIR_ACT1"/>
        </expr>
    </rule>
    <bit pos="0">PPE halted due to an error, which is an OR the 4 signals captured in ERR(0:3). This indication is intended to be reported to the OCC complex as an</bit>
    <bit pos="1">PPE asserted debug trigger. Connected to PPEDBG[FIR_TRIGGER].  May be used by QME hcode to indicate an error to PRD or to induce a checkstop for</bit>
    <bit pos="2">Used for TBD testing or workarounds</bit>
    <bit pos="3">PPE asserted a watchdog timeout condition.</bit>
    <bit pos="4">QME hardware detected its own timeout on the PCB Slave interface and forced a return code of 0x7.  Note: uses the Watchdog TSEL minus 2 bits (watchdog</bit>
    <bit pos="5">Either the Block Copy Engine or QME PPE direct access received an error from  the Fabric.  A BCE error also causes an interrupt to the QME PPE, if it</bit>
    <bit pos="6">SRAM Uncorrectable Error.</bit>
    <bit pos="7">SRAM Correctable Error.  QME received corrected data, but SRAM content is bad until next scrub to that line. (Should be masked in the product;</bit>
    <bit pos="8">Resonant Clock Table array Parity Error.</bit>
    <bit pos="9">Hcode wrote the PIG to request a PCB interrupt before its previously requested interrupt had been completed (meaning PIG[PENDING_SOURCE(0)] = 1 OR</bit>
    <bit pos="10">Scrub timer tick occurred when scrub is still pending (hardware defect or severe configuration error).  Unless the FIT timer is set to smaller than 16</bit>
    <bit pos="11">Refer to ERR bits of the same name to see which Core instance.</bit>
    <bit pos="12">Refer to ERR bits of the same name to see which Core instance.</bit>
    <bit pos="13">PGPE Heartbeat Lost indication from a hardware deadman timer controlled by QHB.  Intended to be reported as an interrupt to QME via action 10.</bit>
    <bit pos="14">Notification that BCE has not made forward progress in the time period corresponding to two scrub timer pulses (regardless of scrub enable).  The BCE</bit>
    <bit pos="15">Resclk TARGET_PSTATE Change Protocol Error. PGPE code bug.</bit>
    <bit pos="16">Unexpected PCB Network or Endpoint Reset occurred when QME was not halted, had an active request to the PCB Slave, or the QME saw a reset without a</bit>
    <bit pos="17">Firmware cleared their Special Wakeup request in SPWU_{OTR|FSP|OCC|HYP}[ SPECIAL_WKUP_REQ] before the SPECIAL_WKUP_DONE was set.</bit>
    <bit pos="18">Indicates a window condition occurred where one firmware component set a new special wakeup right after a different firmware component cleared the</bit>
    <bit pos="19">Any of the Core External Interrupt wakeup sources (os, hyp, msgsnd, msgsndu) are present but disabled by the threads PECE (or UDEE) when it is in Stop</bit>
    <bit pos="20">Any of the Core External Interrupts (os, hyp, msgsnd, msgsndu) are present but the chiplet is deconfigured (based on the partial good region enable</bit>
    <bit pos="21">Reserved</bit>
    <bit pos="22">Data hang was detected in the powerbus logic, caused by a powerbus read command waiting for data that is lost.</bit>
    <bit pos="23">The PPE tried to write a protected address as defined by the SWPR[n] register</bit>
    <bit pos="24">DTC Sequencer read a UE from SRAM, causing it to abort its current sequence and disable itself in QMCR.</bit>
    <bit pos="25">Correctable error detected on incoming data for a PowerBus read.</bit>
    <bit pos="26">UE Detected on incoming data for a PowerBus read.</bit>
    <bit pos="27">SUE Detected on incoming data for a PowerBus read.</bit>
    <bit pos="28">A Powerbus Request address has hit an invalid entry in the TOPOLOGY XLATE TABLE [PBTXTR] REGISTER.  This is an unrecoverable error indicating the</bit>
    <bit pos="29">Parity error detected on a powerbus tag.  Includes combined response ATAG/TTAG parity error as well as a data transaction RTAG parity error.</bit>
    <bit pos="30">Code attempted to write the PIG register when the previous request was still pending i.e. PIG.PENDING_SOURCE(0)=1.</bit>
    <bit pos="31">Set based on the OR of three ERR[LOCAL_ACCESS_*_ERR] bits.</bit>
    <bit pos="32">CE detected on a read to the SSA located in the QME powerbus routing logic.</bit>
    <bit pos="33">UE detected on a read to the SSA located in the QME powerbus routing logic.</bit>
    <bit pos="34">A parity error was detected in one of the CCFG latches present in the Resonant Clock stepper logic in the QME.</bit>
    <bit pos="35">Implemented but not used. Input tied to 0.</bit>
</attn_node>