| Zane Shelley | b9ea93c | 2023-03-10 10:41:41 -0600 | [diff] [blame] | 1 | { |
| 2 | "version": 1, |
| 3 | "model_ec": ["EXPLORER_11", "EXPLORER_20"], |
| 4 | "registers": { |
| 5 | "TLXFIR": { |
| 6 | "instances": { |
| 7 | "0": "0x08012400" |
| 8 | } |
| 9 | }, |
| Caleb Palmer | 94ea8ed | 2024-07-25 14:26:46 -0500 | [diff] [blame] | 10 | "TLXFIR_AND": { |
| 11 | "access": "WO", |
| 12 | "instances": { |
| 13 | "0": "0x08012401" |
| 14 | } |
| 15 | }, |
| 16 | "TLXFIR_OR": { |
| 17 | "access": "WO", |
| 18 | "instances": { |
| 19 | "0": "0x08012402" |
| 20 | } |
| 21 | }, |
| Zane Shelley | b9ea93c | 2023-03-10 10:41:41 -0600 | [diff] [blame] | 22 | "TLXFIR_MASK": { |
| 23 | "instances": { |
| 24 | "0": "0x08012403" |
| 25 | } |
| 26 | }, |
| Caleb Palmer | 94ea8ed | 2024-07-25 14:26:46 -0500 | [diff] [blame] | 27 | "TLXFIR_MASK_AND": { |
| 28 | "access": "WO", |
| 29 | "instances": { |
| 30 | "0": "0x08012404" |
| 31 | } |
| 32 | }, |
| 33 | "TLXFIR_MASK_OR": { |
| 34 | "access": "WO", |
| 35 | "instances": { |
| 36 | "0": "0x08012405" |
| 37 | } |
| 38 | }, |
| Zane Shelley | b9ea93c | 2023-03-10 10:41:41 -0600 | [diff] [blame] | 39 | "TLXFIR_ACT0": { |
| 40 | "instances": { |
| 41 | "0": "0x08012406" |
| 42 | } |
| 43 | }, |
| 44 | "TLXFIR_ACT1": { |
| 45 | "instances": { |
| 46 | "0": "0x08012407" |
| 47 | } |
| 48 | }, |
| 49 | "TLXFIR_WOF": { |
| 50 | "instances": { |
| 51 | "0": "0x08012408" |
| 52 | } |
| 53 | }, |
| 54 | "TLX_ERR_RPT_0": { |
| 55 | "instances": { |
| 56 | "0": "0x0801241C" |
| 57 | } |
| 58 | }, |
| 59 | "TLX_ERR_RPT_1": { |
| 60 | "instances": { |
| 61 | "0": "0x0801241D" |
| 62 | } |
| 63 | }, |
| 64 | "TLX_ERR_RPT_2": { |
| 65 | "instances": { |
| 66 | "0": "0x0801241E" |
| 67 | } |
| 68 | }, |
| 69 | "TLX_ERR_RPT_0_MASK": { |
| 70 | "instances": { |
| 71 | "0": "0x08012414" |
| 72 | } |
| 73 | }, |
| 74 | "TLX_ERR_RPT_1_MASK": { |
| 75 | "instances": { |
| 76 | "0": "0x08012415" |
| 77 | } |
| 78 | }, |
| 79 | "TLX_ERR_RPT_2_MASK": { |
| 80 | "instances": { |
| 81 | "0": "0x08012416" |
| 82 | } |
| 83 | } |
| 84 | }, |
| 85 | "isolation_nodes": { |
| 86 | "TLXFIR": { |
| 87 | "instances": [0], |
| 88 | "rules": [ |
| 89 | { |
| Zane Shelley | 925c3ed | 2023-04-14 13:42:22 -0500 | [diff] [blame] | 90 | "attn_type": ["CHIP_CS"], |
| Zane Shelley | b9ea93c | 2023-03-10 10:41:41 -0600 | [diff] [blame] | 91 | "node_inst": [0], |
| 92 | "expr": { |
| 93 | "expr_type": "and", |
| 94 | "exprs": [ |
| 95 | { |
| 96 | "expr_type": "reg", |
| 97 | "reg_name": "TLXFIR" |
| 98 | }, |
| 99 | { |
| 100 | "expr_type": "not", |
| 101 | "expr": { |
| 102 | "expr_type": "reg", |
| 103 | "reg_name": "TLXFIR_MASK" |
| 104 | } |
| 105 | }, |
| 106 | { |
| 107 | "expr_type": "not", |
| 108 | "expr": { |
| 109 | "expr_type": "reg", |
| 110 | "reg_name": "TLXFIR_ACT0" |
| 111 | } |
| 112 | }, |
| 113 | { |
| 114 | "expr_type": "not", |
| 115 | "expr": { |
| 116 | "expr_type": "reg", |
| 117 | "reg_name": "TLXFIR_ACT1" |
| 118 | } |
| 119 | } |
| 120 | ] |
| 121 | } |
| 122 | }, |
| 123 | { |
| Zane Shelley | 925c3ed | 2023-04-14 13:42:22 -0500 | [diff] [blame] | 124 | "attn_type": ["RECOV"], |
| Zane Shelley | b9ea93c | 2023-03-10 10:41:41 -0600 | [diff] [blame] | 125 | "node_inst": [0], |
| 126 | "expr": { |
| 127 | "expr_type": "and", |
| 128 | "exprs": [ |
| 129 | { |
| 130 | "expr_type": "reg", |
| 131 | "reg_name": "TLXFIR" |
| 132 | }, |
| 133 | { |
| 134 | "expr_type": "not", |
| 135 | "expr": { |
| 136 | "expr_type": "reg", |
| 137 | "reg_name": "TLXFIR_MASK" |
| 138 | } |
| 139 | }, |
| 140 | { |
| 141 | "expr_type": "not", |
| 142 | "expr": { |
| 143 | "expr_type": "reg", |
| 144 | "reg_name": "TLXFIR_ACT0" |
| 145 | } |
| 146 | }, |
| 147 | { |
| 148 | "expr_type": "reg", |
| 149 | "reg_name": "TLXFIR_ACT1" |
| 150 | } |
| 151 | ] |
| 152 | } |
| 153 | }, |
| 154 | { |
| Zane Shelley | 925c3ed | 2023-04-14 13:42:22 -0500 | [diff] [blame] | 155 | "attn_type": ["SP_ATTN"], |
| Zane Shelley | b9ea93c | 2023-03-10 10:41:41 -0600 | [diff] [blame] | 156 | "node_inst": [0], |
| 157 | "expr": { |
| 158 | "expr_type": "and", |
| 159 | "exprs": [ |
| 160 | { |
| 161 | "expr_type": "reg", |
| 162 | "reg_name": "TLXFIR" |
| 163 | }, |
| 164 | { |
| 165 | "expr_type": "not", |
| 166 | "expr": { |
| 167 | "expr_type": "reg", |
| 168 | "reg_name": "TLXFIR_MASK" |
| 169 | } |
| 170 | }, |
| 171 | { |
| 172 | "expr_type": "reg", |
| 173 | "reg_name": "TLXFIR_ACT0" |
| 174 | }, |
| 175 | { |
| 176 | "expr_type": "not", |
| 177 | "expr": { |
| 178 | "expr_type": "reg", |
| 179 | "reg_name": "TLXFIR_ACT1" |
| 180 | } |
| 181 | } |
| 182 | ] |
| 183 | } |
| 184 | } |
| 185 | ], |
| Caleb Palmer | 94ea8ed | 2024-07-25 14:26:46 -0500 | [diff] [blame] | 186 | "op_rules": { |
| 187 | "FIR_SET": { |
| 188 | "op_rule": "atomic_or", |
| 189 | "reg_name": "TLXFIR_OR" |
| 190 | }, |
| 191 | "FIR_CLEAR": { |
| 192 | "op_rule": "atomic_and", |
| 193 | "reg_name": "TLXFIR_AND" |
| 194 | }, |
| 195 | "MASK_SET": { |
| 196 | "op_rule": "atomic_or", |
| 197 | "reg_name": "TLXFIR_MASK_OR" |
| 198 | }, |
| 199 | "MASK_CLEAR": { |
| 200 | "op_rule": "atomic_and", |
| 201 | "reg_name": "TLXFIR_MASK_AND" |
| 202 | } |
| 203 | }, |
| Zane Shelley | b9ea93c | 2023-03-10 10:41:41 -0600 | [diff] [blame] | 204 | "bits": { |
| 205 | "0": { |
| 206 | "desc": "Info reg parity error" |
| 207 | }, |
| 208 | "1": { |
| 209 | "desc": "Ctrl reg parity error" |
| 210 | }, |
| 211 | "2": { |
| 212 | "desc": "TLX VC0 return credit counter overflow" |
| 213 | }, |
| 214 | "3": { |
| 215 | "desc": "TLX VC1 return credit counter overflow" |
| 216 | }, |
| 217 | "4": { |
| 218 | "desc": "TLX dcp0 return credit counter overflow" |
| 219 | }, |
| 220 | "5": { |
| 221 | "desc": "TLX dcp1 return credit counter overflow" |
| 222 | }, |
| 223 | "6": { |
| 224 | "desc": "TLX credit management block error" |
| 225 | }, |
| 226 | "7": { |
| 227 | "desc": "TLX credit management block parity error" |
| 228 | }, |
| 229 | "8": { |
| 230 | "desc": "TLXT fatal parity error" |
| 231 | }, |
| 232 | "9": { |
| 233 | "desc": "TLXT recoverable error", |
| 234 | "child_node": { |
| 235 | "name": "TLX_ERR_RPT_1" |
| 236 | } |
| 237 | }, |
| 238 | "10": { |
| 239 | "desc": "TLXT configuration error" |
| 240 | }, |
| 241 | "11": { |
| 242 | "desc": "TLXT informational parity error" |
| 243 | }, |
| 244 | "12": { |
| 245 | "desc": "TLXT hard error" |
| 246 | }, |
| 247 | "13:15": { |
| 248 | "desc": "Reserved" |
| 249 | }, |
| 250 | "16": { |
| 251 | "desc": "Corrupted pad mem pattern" |
| 252 | }, |
| 253 | "17": { |
| 254 | "desc": "Downstream OC parity error" |
| 255 | }, |
| 256 | "18": { |
| 257 | "desc": "OC malformed" |
| 258 | }, |
| 259 | "19": { |
| 260 | "desc": "OC protocol error" |
| 261 | }, |
| 262 | "20": { |
| 263 | "desc": "Address translate error" |
| 264 | }, |
| 265 | "21": { |
| 266 | "desc": "Metadata unc or data parity error" |
| 267 | }, |
| 268 | "22": { |
| 269 | "desc": "OC unsupported group 2" |
| 270 | }, |
| 271 | "23": { |
| 272 | "desc": "OC unsupported group 1" |
| 273 | }, |
| 274 | "24": { |
| 275 | "desc": "Bit flip control error" |
| 276 | }, |
| 277 | "25": { |
| 278 | "desc": "Control HW error" |
| 279 | }, |
| 280 | "26": { |
| 281 | "desc": "ECC corrected and others" |
| 282 | }, |
| 283 | "27": { |
| 284 | "desc": "Trace stop" |
| 285 | }, |
| 286 | "28": { |
| 287 | "desc": "Internal SCOM error" |
| 288 | }, |
| 289 | "29": { |
| 290 | "desc": "Internal SCOM error clone" |
| 291 | } |
| 292 | }, |
| 293 | "capture_groups": [ |
| 294 | { |
| 295 | "group_name": "TLXFIR", |
| 296 | "group_inst": { |
| 297 | "0": 0 |
| 298 | } |
| 299 | } |
| 300 | ] |
| 301 | } |
| 302 | }, |
| 303 | "capture_groups": { |
| 304 | "TLXFIR": [ |
| 305 | { |
| 306 | "reg_name": "TLX_ERR_RPT_0", |
| 307 | "reg_inst": { |
| 308 | "0": 0 |
| 309 | } |
| 310 | }, |
| 311 | { |
| 312 | "reg_name": "TLX_ERR_RPT_1", |
| 313 | "reg_inst": { |
| 314 | "0": 0 |
| 315 | } |
| 316 | }, |
| 317 | { |
| 318 | "reg_name": "TLX_ERR_RPT_2", |
| 319 | "reg_inst": { |
| 320 | "0": 0 |
| 321 | } |
| 322 | }, |
| 323 | { |
| 324 | "reg_name": "TLX_ERR_RPT_0_MASK", |
| 325 | "reg_inst": { |
| 326 | "0": 0 |
| 327 | } |
| 328 | }, |
| 329 | { |
| 330 | "reg_name": "TLX_ERR_RPT_1_MASK", |
| 331 | "reg_inst": { |
| 332 | "0": 0 |
| 333 | } |
| 334 | }, |
| 335 | { |
| 336 | "reg_name": "TLX_ERR_RPT_2_MASK", |
| 337 | "reg_inst": { |
| 338 | "0": 0 |
| 339 | } |
| 340 | } |
| 341 | ] |
| 342 | } |
| 343 | } |