Zane Shelley | c928f94 | 2021-07-09 14:32:58 -0500 | [diff] [blame] | 1 | <?xml version="1.0" encoding="UTF-8"?> |
| 2 | <attn_node name="OMI_DL_FIR" model_ec="EXPLORER_11,EXPLORER_20" reg_type="SCOM"> |
| 3 | |
| 4 | <local_fir name="OMI_DL_FIR" config="W"> |
| 5 | <instance reg_inst="0" addr="0x08012800" /> |
| 6 | <action attn_type="UCS" config="00" /> |
| 7 | <action attn_type="RE" config="01" /> |
| 8 | <action attn_type="HA" config="10" /> |
| 9 | </local_fir> |
| 10 | |
| 11 | <register name="CMN_CONFIG"> |
| 12 | <instance reg_inst="0" addr="0x0801280E" /> |
| 13 | </register> |
| 14 | |
| 15 | <register name="PMU_CNTR"> |
| 16 | <instance reg_inst="0" addr="0x0801280F" /> |
| 17 | </register> |
| 18 | |
Caleb Palmer | c3aa164 | 2022-11-28 14:44:21 -0600 | [diff] [blame] | 19 | <register name="OMI_DL_CONFIG0"> |
| 20 | <instance reg_inst="0" addr="0x08012810" /> |
| 21 | </register> |
| 22 | |
| 23 | <register name="OMI_DL_CONFIG1"> |
| 24 | <instance reg_inst="0" addr="0x08012811" /> |
| 25 | </register> |
| 26 | |
| 27 | <register name="OMI_DL_ERR_MASK"> |
| 28 | <instance reg_inst="0" addr="0x08012812" /> |
| 29 | </register> |
| 30 | |
| 31 | <register name="OMI_DL_ERR_RPT"> |
| 32 | <instance reg_inst="0" addr="0x08012813" /> |
| 33 | </register> |
| 34 | |
| 35 | <register name="OMI_DL_ERR_CAPTURE"> |
| 36 | <instance reg_inst="0" addr="0x08012814" /> |
| 37 | </register> |
| 38 | |
| 39 | <register name="OMI_DL_EDPL_MAX_COUNT"> |
| 40 | <instance reg_inst="0" addr="0x08012815" /> |
| 41 | </register> |
| 42 | |
| 43 | <register name="OMI_DL_STATUS"> |
| 44 | <instance reg_inst="0" addr="0x08012816" /> |
| 45 | </register> |
| 46 | |
| 47 | <register name="OMI_DL_TRAINING_STATUS"> |
| 48 | <instance reg_inst="0" addr="0x08012817" /> |
| 49 | </register> |
| 50 | |
| 51 | <register name="OMI_DL_DLX_CONFIG"> |
| 52 | <instance reg_inst="0" addr="0x08012818" /> |
| 53 | </register> |
| 54 | |
| 55 | <register name="OMI_DL_DLX_INFO"> |
| 56 | <instance reg_inst="0" addr="0x08012819" /> |
| 57 | </register> |
| 58 | |
| 59 | <register name="OMI_DL_ERR_ACTION"> |
| 60 | <instance reg_inst="0" addr="0x0801281D" /> |
| 61 | </register> |
| 62 | |
| 63 | <register name="OMI_DL_DEBUG_AID"> |
| 64 | <instance reg_inst="0" addr="0x0801281E" /> |
| 65 | </register> |
| 66 | |
| 67 | <register name="OMI_DL_CYA_BITS"> |
| 68 | <instance reg_inst="0" addr="0x0801281F" /> |
| 69 | </register> |
| 70 | |
Zane Shelley | c928f94 | 2021-07-09 14:32:58 -0500 | [diff] [blame] | 71 | <capture_group node_inst="0"> |
Caleb Palmer | c3aa164 | 2022-11-28 14:44:21 -0600 | [diff] [blame] | 72 | <capture_register reg_name="CMN_CONFIG" reg_inst="0" /> |
| 73 | <capture_register reg_name="PMU_CNTR" reg_inst="0" /> |
| 74 | <capture_register reg_name="OMI_DL_CONFIG0" reg_inst="0" /> |
| 75 | <capture_register reg_name="OMI_DL_CONFIG1" reg_inst="0" /> |
| 76 | <capture_register reg_name="OMI_DL_ERR_MASK" reg_inst="0" /> |
| 77 | <capture_register reg_name="OMI_DL_ERR_RPT" reg_inst="0" /> |
| 78 | <capture_register reg_name="OMI_DL_ERR_CAPTURE" reg_inst="0" /> |
| 79 | <capture_register reg_name="OMI_DL_EDPL_MAX_COUNT" reg_inst="0" /> |
| 80 | <capture_register reg_name="OMI_DL_STATUS" reg_inst="0" /> |
| 81 | <capture_register reg_name="OMI_DL_TRAINING_STATUS" reg_inst="0" /> |
| 82 | <capture_register reg_name="OMI_DL_DLX_CONFIG" reg_inst="0" /> |
| 83 | <capture_register reg_name="OMI_DL_DLX_INFO" reg_inst="0" /> |
| 84 | <capture_register reg_name="OMI_DL_ERR_ACTION" reg_inst="0" /> |
| 85 | <capture_register reg_name="OMI_DL_DEBUG_AID" reg_inst="0" /> |
| 86 | <capture_register reg_name="OMI_DL_CYA_BITS" reg_inst="0" /> |
Zane Shelley | c928f94 | 2021-07-09 14:32:58 -0500 | [diff] [blame] | 87 | </capture_group> |
| 88 | |
Caleb Palmer | c3aa164 | 2022-11-28 14:44:21 -0600 | [diff] [blame] | 89 | <bit pos= "0" child_node="OMI_DL_ERR_RPT" node_inst="0">OMI-DL0 fatal error</bit> |
| 90 | <bit pos= "1">OMI-DL0 UE on data flit</bit> |
| 91 | <bit pos= "2">OMI-DL0 CE on TL flit</bit> |
| 92 | <bit pos= "3">OMI-DL0 detected a CRC error</bit> |
| 93 | <bit pos= "4">OMI-DL0 received a nack</bit> |
| 94 | <bit pos= "5">OMI-DL0 running in degraded mode</bit> |
| 95 | <bit pos= "6">OMI-DL0 parity error detection on a lane</bit> |
| 96 | <bit pos= "7">OMI-DL0 retrained due to no forward progress</bit> |
| 97 | <bit pos= "8">OMI-DL0 remote side initiated a retrain</bit> |
| 98 | <bit pos= "9">OMI-DL0 retrain due to internal error or software</bit> |
| 99 | <bit pos="10">OMI-DL0 threshold reached</bit> |
| 100 | <bit pos="11">OMI-DL0 trained</bit> |
| 101 | <bit pos="12">OMI-DL0 endpoint error bit 0</bit> |
| 102 | <bit pos="13">OMI-DL0 endpoint error bit 1</bit> |
| 103 | <bit pos="14">OMI-DL0 endpoint error bit 2</bit> |
| 104 | <bit pos="15">OMI-DL0 endpoint error bit 3</bit> |
| 105 | <bit pos="16">OMI-DL0 endpoint error bit 4</bit> |
| 106 | <bit pos="17">OMI-DL0 endpoint error bit 5</bit> |
| 107 | <bit pos="18">OMI-DL0 endpoint error bit 6</bit> |
| 108 | <bit pos="19">OMI-DL0 endpoint error bit 7</bit> |
Zane Shelley | c928f94 | 2021-07-09 14:32:58 -0500 | [diff] [blame] | 109 | <bit pos="20:39">OMI-DL1</bit> |
| 110 | <bit pos="40:59">OMI-DL2</bit> |
| 111 | <bit pos="60">Performance monitor wrapped</bit> |
| 112 | <bit pos="61">reserved</bit> |
| 113 | <bit pos="62">LFIR internal parity error</bit> |
| 114 | <bit pos="63">SCOM Satellite Error</bit> |
| 115 | |
| 116 | </attn_node> |