Zane Shelley | abc51c2 | 2020-11-09 21:35:35 -0600 | [diff] [blame] | 1 | <?xml version="1.0" encoding="UTF-8"?> |
Zane Shelley | f8a726b | 2020-12-16 21:29:32 -0600 | [diff] [blame] | 2 | <attn_node model_ec="P10_20" name="EQ_CORE_FIR" reg_type="SCOM"> |
Zane Shelley | abc51c2 | 2020-11-09 21:35:35 -0600 | [diff] [blame] | 3 | <register name="EQ_CORE_FIR"> |
| 4 | <instance addr="0x20028440" reg_inst="0"/> |
| 5 | <instance addr="0x20024440" reg_inst="1"/> |
| 6 | <instance addr="0x20022440" reg_inst="2"/> |
| 7 | <instance addr="0x20021440" reg_inst="3"/> |
| 8 | <instance addr="0x21028440" reg_inst="4"/> |
| 9 | <instance addr="0x21024440" reg_inst="5"/> |
| 10 | <instance addr="0x21022440" reg_inst="6"/> |
| 11 | <instance addr="0x21021440" reg_inst="7"/> |
| 12 | <instance addr="0x22028440" reg_inst="8"/> |
| 13 | <instance addr="0x22024440" reg_inst="9"/> |
| 14 | <instance addr="0x22022440" reg_inst="10"/> |
| 15 | <instance addr="0x22021440" reg_inst="11"/> |
| 16 | <instance addr="0x23028440" reg_inst="12"/> |
| 17 | <instance addr="0x23024440" reg_inst="13"/> |
| 18 | <instance addr="0x23022440" reg_inst="14"/> |
| 19 | <instance addr="0x23021440" reg_inst="15"/> |
| 20 | <instance addr="0x24028440" reg_inst="16"/> |
| 21 | <instance addr="0x24024440" reg_inst="17"/> |
| 22 | <instance addr="0x24022440" reg_inst="18"/> |
| 23 | <instance addr="0x24021440" reg_inst="19"/> |
| 24 | <instance addr="0x25028440" reg_inst="20"/> |
| 25 | <instance addr="0x25024440" reg_inst="21"/> |
| 26 | <instance addr="0x25022440" reg_inst="22"/> |
| 27 | <instance addr="0x25021440" reg_inst="23"/> |
| 28 | <instance addr="0x26028440" reg_inst="24"/> |
| 29 | <instance addr="0x26024440" reg_inst="25"/> |
| 30 | <instance addr="0x26022440" reg_inst="26"/> |
| 31 | <instance addr="0x26021440" reg_inst="27"/> |
| 32 | <instance addr="0x27028440" reg_inst="28"/> |
| 33 | <instance addr="0x27024440" reg_inst="29"/> |
| 34 | <instance addr="0x27022440" reg_inst="30"/> |
| 35 | <instance addr="0x27021440" reg_inst="31"/> |
| 36 | </register> |
| 37 | <register name="EQ_CORE_FIR_MASK"> |
| 38 | <instance addr="0x20028443" reg_inst="0"/> |
| 39 | <instance addr="0x20024443" reg_inst="1"/> |
| 40 | <instance addr="0x20022443" reg_inst="2"/> |
| 41 | <instance addr="0x20021443" reg_inst="3"/> |
| 42 | <instance addr="0x21028443" reg_inst="4"/> |
| 43 | <instance addr="0x21024443" reg_inst="5"/> |
| 44 | <instance addr="0x21022443" reg_inst="6"/> |
| 45 | <instance addr="0x21021443" reg_inst="7"/> |
| 46 | <instance addr="0x22028443" reg_inst="8"/> |
| 47 | <instance addr="0x22024443" reg_inst="9"/> |
| 48 | <instance addr="0x22022443" reg_inst="10"/> |
| 49 | <instance addr="0x22021443" reg_inst="11"/> |
| 50 | <instance addr="0x23028443" reg_inst="12"/> |
| 51 | <instance addr="0x23024443" reg_inst="13"/> |
| 52 | <instance addr="0x23022443" reg_inst="14"/> |
| 53 | <instance addr="0x23021443" reg_inst="15"/> |
| 54 | <instance addr="0x24028443" reg_inst="16"/> |
| 55 | <instance addr="0x24024443" reg_inst="17"/> |
| 56 | <instance addr="0x24022443" reg_inst="18"/> |
| 57 | <instance addr="0x24021443" reg_inst="19"/> |
| 58 | <instance addr="0x25028443" reg_inst="20"/> |
| 59 | <instance addr="0x25024443" reg_inst="21"/> |
| 60 | <instance addr="0x25022443" reg_inst="22"/> |
| 61 | <instance addr="0x25021443" reg_inst="23"/> |
| 62 | <instance addr="0x26028443" reg_inst="24"/> |
| 63 | <instance addr="0x26024443" reg_inst="25"/> |
| 64 | <instance addr="0x26022443" reg_inst="26"/> |
| 65 | <instance addr="0x26021443" reg_inst="27"/> |
| 66 | <instance addr="0x27028443" reg_inst="28"/> |
| 67 | <instance addr="0x27024443" reg_inst="29"/> |
| 68 | <instance addr="0x27022443" reg_inst="30"/> |
| 69 | <instance addr="0x27021443" reg_inst="31"/> |
| 70 | </register> |
| 71 | <register name="EQ_CORE_FIR_ACT0"> |
| 72 | <instance addr="0x20028446" reg_inst="0"/> |
| 73 | <instance addr="0x20024446" reg_inst="1"/> |
| 74 | <instance addr="0x20022446" reg_inst="2"/> |
| 75 | <instance addr="0x20021446" reg_inst="3"/> |
| 76 | <instance addr="0x21028446" reg_inst="4"/> |
| 77 | <instance addr="0x21024446" reg_inst="5"/> |
| 78 | <instance addr="0x21022446" reg_inst="6"/> |
| 79 | <instance addr="0x21021446" reg_inst="7"/> |
| 80 | <instance addr="0x22028446" reg_inst="8"/> |
| 81 | <instance addr="0x22024446" reg_inst="9"/> |
| 82 | <instance addr="0x22022446" reg_inst="10"/> |
| 83 | <instance addr="0x22021446" reg_inst="11"/> |
| 84 | <instance addr="0x23028446" reg_inst="12"/> |
| 85 | <instance addr="0x23024446" reg_inst="13"/> |
| 86 | <instance addr="0x23022446" reg_inst="14"/> |
| 87 | <instance addr="0x23021446" reg_inst="15"/> |
| 88 | <instance addr="0x24028446" reg_inst="16"/> |
| 89 | <instance addr="0x24024446" reg_inst="17"/> |
| 90 | <instance addr="0x24022446" reg_inst="18"/> |
| 91 | <instance addr="0x24021446" reg_inst="19"/> |
| 92 | <instance addr="0x25028446" reg_inst="20"/> |
| 93 | <instance addr="0x25024446" reg_inst="21"/> |
| 94 | <instance addr="0x25022446" reg_inst="22"/> |
| 95 | <instance addr="0x25021446" reg_inst="23"/> |
| 96 | <instance addr="0x26028446" reg_inst="24"/> |
| 97 | <instance addr="0x26024446" reg_inst="25"/> |
| 98 | <instance addr="0x26022446" reg_inst="26"/> |
| 99 | <instance addr="0x26021446" reg_inst="27"/> |
| 100 | <instance addr="0x27028446" reg_inst="28"/> |
| 101 | <instance addr="0x27024446" reg_inst="29"/> |
| 102 | <instance addr="0x27022446" reg_inst="30"/> |
| 103 | <instance addr="0x27021446" reg_inst="31"/> |
| 104 | </register> |
| 105 | <register name="EQ_CORE_FIR_ACT1"> |
| 106 | <instance addr="0x20028447" reg_inst="0"/> |
| 107 | <instance addr="0x20024447" reg_inst="1"/> |
| 108 | <instance addr="0x20022447" reg_inst="2"/> |
| 109 | <instance addr="0x20021447" reg_inst="3"/> |
| 110 | <instance addr="0x21028447" reg_inst="4"/> |
| 111 | <instance addr="0x21024447" reg_inst="5"/> |
| 112 | <instance addr="0x21022447" reg_inst="6"/> |
| 113 | <instance addr="0x21021447" reg_inst="7"/> |
| 114 | <instance addr="0x22028447" reg_inst="8"/> |
| 115 | <instance addr="0x22024447" reg_inst="9"/> |
| 116 | <instance addr="0x22022447" reg_inst="10"/> |
| 117 | <instance addr="0x22021447" reg_inst="11"/> |
| 118 | <instance addr="0x23028447" reg_inst="12"/> |
| 119 | <instance addr="0x23024447" reg_inst="13"/> |
| 120 | <instance addr="0x23022447" reg_inst="14"/> |
| 121 | <instance addr="0x23021447" reg_inst="15"/> |
| 122 | <instance addr="0x24028447" reg_inst="16"/> |
| 123 | <instance addr="0x24024447" reg_inst="17"/> |
| 124 | <instance addr="0x24022447" reg_inst="18"/> |
| 125 | <instance addr="0x24021447" reg_inst="19"/> |
| 126 | <instance addr="0x25028447" reg_inst="20"/> |
| 127 | <instance addr="0x25024447" reg_inst="21"/> |
| 128 | <instance addr="0x25022447" reg_inst="22"/> |
| 129 | <instance addr="0x25021447" reg_inst="23"/> |
| 130 | <instance addr="0x26028447" reg_inst="24"/> |
| 131 | <instance addr="0x26024447" reg_inst="25"/> |
| 132 | <instance addr="0x26022447" reg_inst="26"/> |
| 133 | <instance addr="0x26021447" reg_inst="27"/> |
| 134 | <instance addr="0x27028447" reg_inst="28"/> |
| 135 | <instance addr="0x27024447" reg_inst="29"/> |
| 136 | <instance addr="0x27022447" reg_inst="30"/> |
| 137 | <instance addr="0x27021447" reg_inst="31"/> |
| 138 | </register> |
| 139 | <register name="EQ_CORE_FIR_WOF"> |
| 140 | <instance addr="0x20028448" reg_inst="0"/> |
| 141 | <instance addr="0x20024448" reg_inst="1"/> |
| 142 | <instance addr="0x20022448" reg_inst="2"/> |
| 143 | <instance addr="0x20021448" reg_inst="3"/> |
| 144 | <instance addr="0x21028448" reg_inst="4"/> |
| 145 | <instance addr="0x21024448" reg_inst="5"/> |
| 146 | <instance addr="0x21022448" reg_inst="6"/> |
| 147 | <instance addr="0x21021448" reg_inst="7"/> |
| 148 | <instance addr="0x22028448" reg_inst="8"/> |
| 149 | <instance addr="0x22024448" reg_inst="9"/> |
| 150 | <instance addr="0x22022448" reg_inst="10"/> |
| 151 | <instance addr="0x22021448" reg_inst="11"/> |
| 152 | <instance addr="0x23028448" reg_inst="12"/> |
| 153 | <instance addr="0x23024448" reg_inst="13"/> |
| 154 | <instance addr="0x23022448" reg_inst="14"/> |
| 155 | <instance addr="0x23021448" reg_inst="15"/> |
| 156 | <instance addr="0x24028448" reg_inst="16"/> |
| 157 | <instance addr="0x24024448" reg_inst="17"/> |
| 158 | <instance addr="0x24022448" reg_inst="18"/> |
| 159 | <instance addr="0x24021448" reg_inst="19"/> |
| 160 | <instance addr="0x25028448" reg_inst="20"/> |
| 161 | <instance addr="0x25024448" reg_inst="21"/> |
| 162 | <instance addr="0x25022448" reg_inst="22"/> |
| 163 | <instance addr="0x25021448" reg_inst="23"/> |
| 164 | <instance addr="0x26028448" reg_inst="24"/> |
| 165 | <instance addr="0x26024448" reg_inst="25"/> |
| 166 | <instance addr="0x26022448" reg_inst="26"/> |
| 167 | <instance addr="0x26021448" reg_inst="27"/> |
| 168 | <instance addr="0x27028448" reg_inst="28"/> |
| 169 | <instance addr="0x27024448" reg_inst="29"/> |
| 170 | <instance addr="0x27022448" reg_inst="30"/> |
| 171 | <instance addr="0x27021448" reg_inst="31"/> |
| 172 | </register> |
| 173 | <rule attn_type="CS" node_inst="0:31"> |
| 174 | <!-- FIR & ~MASK & ~ACT0 & ~ACT1 --> |
| 175 | <expr type="and"> |
| 176 | <expr type="reg" value1="EQ_CORE_FIR"/> |
| 177 | <expr type="not"> |
| 178 | <expr type="reg" value1="EQ_CORE_FIR_MASK"/> |
| 179 | </expr> |
| 180 | <expr type="not"> |
| 181 | <expr type="reg" value1="EQ_CORE_FIR_ACT0"/> |
| 182 | </expr> |
| 183 | <expr type="not"> |
| 184 | <expr type="reg" value1="EQ_CORE_FIR_ACT1"/> |
| 185 | </expr> |
| 186 | </expr> |
| 187 | </rule> |
| 188 | <rule attn_type="RE" node_inst="0:31"> |
| 189 | <!-- WOF & ~MASK & ~ACT0 & ACT1 --> |
| 190 | <expr type="and"> |
| 191 | <expr type="reg" value1="EQ_CORE_FIR_WOF"/> |
| 192 | <expr type="not"> |
| 193 | <expr type="reg" value1="EQ_CORE_FIR_MASK"/> |
| 194 | </expr> |
| 195 | <expr type="not"> |
| 196 | <expr type="reg" value1="EQ_CORE_FIR_ACT0"/> |
| 197 | </expr> |
| 198 | <expr type="reg" value1="EQ_CORE_FIR_ACT1"/> |
| 199 | </expr> |
| 200 | </rule> |
| 201 | <rule attn_type="UCS" node_inst="0:31"> |
| 202 | <!-- FIR & ~MASK & ACT0 & ACT1 --> |
| 203 | <expr type="and"> |
| 204 | <expr type="reg" value1="EQ_CORE_FIR"/> |
| 205 | <expr type="not"> |
| 206 | <expr type="reg" value1="EQ_CORE_FIR_MASK"/> |
| 207 | </expr> |
| 208 | <expr type="reg" value1="EQ_CORE_FIR_ACT0"/> |
| 209 | <expr type="reg" value1="EQ_CORE_FIR_ACT1"/> |
| 210 | </expr> |
| 211 | </rule> |
| 212 | <bit pos="0">IFU SRAM recoverable error (ICACHE parity error, etc)</bit> |
| 213 | <bit pos="1">TC checkstop</bit> |
| 214 | <bit pos="2">IFU RegFile recoverable error</bit> |
| 215 | <bit pos="3">IFU RegFile core checkstop</bit> |
| 216 | <bit pos="4">IFU logic recoverable error</bit> |
| 217 | <bit pos="5">IFU logic core checkstop</bit> |
| 218 | <bit pos="6">reserved</bit> |
| 219 | <bit pos="7">VSU Inference Accumulator recoverable error</bit> |
| 220 | <bit pos="8">Recovery core checkstop</bit> |
| 221 | <bit pos="9">VSU Slice Targeted File (STF) recoverable error</bit> |
| 222 | <bit pos="10">reserved</bit> |
| 223 | <bit pos="11">ISU logic recoverable error</bit> |
| 224 | <bit pos="12">ISU logic core checkstop</bit> |
Zane Shelley | f8a726b | 2020-12-16 21:29:32 -0600 | [diff] [blame] | 225 | <bit pos="13">reserved</bit> |
Zane Shelley | abc51c2 | 2020-11-09 21:35:35 -0600 | [diff] [blame] | 226 | <bit pos="14">MCHK received while ME=0 - non recoverable</bit> |
| 227 | <bit pos="15">UE from L2</bit> |
| 228 | <bit pos="16">Number of UEs from L2 above threshold</bit> |
| 229 | <bit pos="17">UE on CI load</bit> |
| 230 | <bit pos="18">MMU TLB parity recoverable error</bit> |
| 231 | <bit pos="19">MMU SLB parity recoverable error</bit> |
| 232 | <bit pos="20">reserved</bit> |
| 233 | <bit pos="21">MMU CXT recoverable error</bit> |
| 234 | <bit pos="22">MMU logic core checkstop</bit> |
| 235 | <bit pos="23">MMU system checkstop</bit> |
| 236 | <bit pos="24">VSU logic recoverable error</bit> |
| 237 | <bit pos="25">VSU logic core checkstop</bit> |
| 238 | <bit pos="26">Thread in maintenance mode and receives recovery request</bit> |
| 239 | <bit pos="27">reserved</bit> |
| 240 | <bit pos="28">PC system checkstop - Recoverable error received when recovery disabled</bit> |
| 241 | <bit pos="29">LSU SRAM recoverable error (DCACHE parity error, ERAT parity error, etc)</bit> |
| 242 | <bit pos="30">LSU set deleted</bit> |
| 243 | <bit pos="31">LSU RegFile recoverable error</bit> |
| 244 | <bit pos="32">LSU RegFile core checkstop</bit> |
| 245 | <bit pos="33">MMU TLB multi hit error occurred</bit> |
| 246 | <bit pos="34">MMU SLB multi hit error occurred</bit> |
| 247 | <bit pos="35">LSU ERAT multi hit error occurred</bit> |
| 248 | <bit pos="36">PC forward progress error</bit> |
| 249 | <bit pos="37">LSU logic recoverable error</bit> |
| 250 | <bit pos="38">LSU logic core checkstop</bit> |
| 251 | <bit pos="39">reserved</bit> |
| 252 | <bit pos="40">reserved</bit> |
| 253 | <bit pos="41">LSU system checkstop</bit> |
| 254 | <bit pos="42">reserved</bit> |
| 255 | <bit pos="43">PC thread hang recoverable error</bit> |
| 256 | <bit pos="44">reserved</bit> |
| 257 | <bit pos="45">PC logic checkstop</bit> |
| 258 | <bit pos="46">PC TimeBase Facility checkstop</bit> |
| 259 | <bit pos="47">PC TimeBase Facility checkstop</bit> |
| 260 | <bit pos="48">reserved</bit> |
| 261 | <bit pos="49">reserved</bit> |
| 262 | <bit pos="50">reserved</bit> |
| 263 | <bit pos="51">reserved</bit> |
| 264 | <bit pos="52">Hang Recovery Failed</bit> |
| 265 | <bit pos="53">Core Hang detected</bit> |
| 266 | <bit pos="54">reserved</bit> |
| 267 | <bit pos="55">Nest Hang detected</bit> |
| 268 | <bit pos="56">Other Core Chiplet recoverable error</bit> |
| 269 | <bit pos="57">Other Core Chiplet core checkstop</bit> |
| 270 | <bit pos="58">Other Core Chiplet system checkstop</bit> |
| 271 | <bit pos="59">SCOM satellite error detected</bit> |
| 272 | <bit pos="60">Debug Trigger error inject</bit> |
| 273 | <bit pos="61">SCOM or Firmware recoverable error inject</bit> |
| 274 | <bit pos="62">Firmware checkstop error inject</bit> |
| 275 | <bit pos="63">PHYP checkstop via SPRC/SPRD</bit> |
| 276 | </attn_node> |