xml/p10/node_mc_ustl_fir_p10_10.xml

<?xml version="1.0" encoding="UTF-8"?>
<attn_node model_ec="P10_10" name="MC_USTL_FIR" reg_type="SCOM">
    <local_fir config="W2" name="MC_USTL_FIR">
        <instance addr="0x0C010E00" reg_inst="0"/>
        <instance addr="0x0C010E40" reg_inst="1"/>
        <instance addr="0x0D010E00" reg_inst="2"/>
        <instance addr="0x0D010E40" reg_inst="3"/>
        <instance addr="0x0E010E00" reg_inst="4"/>
        <instance addr="0x0E010E40" reg_inst="5"/>
        <instance addr="0x0F010E00" reg_inst="6"/>
        <instance addr="0x0F010E40" reg_inst="7"/>
        <action attn_type="CS" config="000"/>
        <action attn_type="RE" config="010"/>
        <action attn_type="SPA" config="100"/>
        <action attn_type="UCS" config="110"/>
        <action attn_type="HA" config="001"/>
    </local_fir>
    <register name="MC_USTL_ERR_RPT_0">
        <instance addr="0x0C010E0E" reg_inst="0"/>
        <instance addr="0x0C010E4E" reg_inst="1"/>
        <instance addr="0x0D010E0E" reg_inst="2"/>
        <instance addr="0x0D010E4E" reg_inst="3"/>
        <instance addr="0x0E010E0E" reg_inst="4"/>
        <instance addr="0x0E010E4E" reg_inst="5"/>
        <instance addr="0x0F010E0E" reg_inst="6"/>
        <instance addr="0x0F010E4E" reg_inst="7"/>
    </register>
    <register name="MC_USTL_LOL_DROP">
        <instance addr="0x0C010E11" reg_inst="0"/>
        <instance addr="0x0C010E51" reg_inst="1"/>
        <instance addr="0x0D010E11" reg_inst="2"/>
        <instance addr="0x0D010E51" reg_inst="3"/>
        <instance addr="0x0E010E11" reg_inst="4"/>
        <instance addr="0x0E010E51" reg_inst="5"/>
        <instance addr="0x0F010E11" reg_inst="6"/>
        <instance addr="0x0F010E51" reg_inst="7"/>
    </register>
    <register name="MC_USTL_LOL_MASK">
        <instance addr="0x0C010E12" reg_inst="0"/>
        <instance addr="0x0C010E52" reg_inst="1"/>
        <instance addr="0x0D010E12" reg_inst="2"/>
        <instance addr="0x0D010E52" reg_inst="3"/>
        <instance addr="0x0E010E12" reg_inst="4"/>
        <instance addr="0x0E010E52" reg_inst="5"/>
        <instance addr="0x0F010E12" reg_inst="6"/>
        <instance addr="0x0F010E52" reg_inst="7"/>
    </register>
    <register name="MC_USTL_FAIL_MASK">
        <instance addr="0x0C010E13" reg_inst="0"/>
        <instance addr="0x0C010E53" reg_inst="1"/>
        <instance addr="0x0D010E13" reg_inst="2"/>
        <instance addr="0x0D010E53" reg_inst="3"/>
        <instance addr="0x0E010E13" reg_inst="4"/>
        <instance addr="0x0E010E53" reg_inst="5"/>
        <instance addr="0x0F010E13" reg_inst="6"/>
        <instance addr="0x0F010E53" reg_inst="7"/>
    </register>
    <register name="MC_USTL_ERR_RPT_1">
        <instance addr="0x0C010E16" reg_inst="0"/>
        <instance addr="0x0C010E56" reg_inst="1"/>
        <instance addr="0x0D010E16" reg_inst="2"/>
        <instance addr="0x0D010E56" reg_inst="3"/>
        <instance addr="0x0E010E16" reg_inst="4"/>
        <instance addr="0x0E010E56" reg_inst="5"/>
        <instance addr="0x0F010E16" reg_inst="6"/>
        <instance addr="0x0F010E56" reg_inst="7"/>
    </register>
    <capture_group node_inst="0:7">
        <capture_register reg_inst="0:7" reg_name="MC_USTL_ERR_RPT_0" />
        <capture_register reg_inst="0:7" reg_name="MC_USTL_LOL_DROP" />
        <capture_register reg_inst="0:7" reg_name="MC_USTL_LOL_MASK" />
        <capture_register reg_inst="0:7" reg_name="MC_USTL_FAIL_MASK" />
        <capture_register reg_inst="0:7" reg_name="MC_USTL_ERR_RPT_1" />
    </capture_group>
    <bit pos="0">Unexpected Flit Data showed up for Chana</bit>
    <bit pos="1">Unexpected Flit Data showed up for Chanb</bit>
    <bit pos="2">A unsupported template for a command flit for chana</bit>
    <bit pos="3">A unsupported template for a command flit for chanb</bit>
    <bit pos="4">Reserved</bit>
    <bit pos="5">Reserved</bit>
    <bit pos="6">WDF CE detected on buffer output</bit>
    <bit pos="7">WDF UE detected on buffer output</bit>
    <bit pos="8">WDF SUE detected on buffer output</bit>
    <bit pos="9">WDF buffer overrun detected</bit>
    <bit pos="10">WDF detected parity on USTL tag interface</bit>
    <bit pos="11">WDF detected a scom sequencer error</bit>
    <bit pos="12">WDF detected a pwctl sequencer error</bit>
    <bit pos="13">WDF detected a parity error on the misc_reg scom register</bit>
    <bit pos="14">Parity Error detected in WDF for CL pop</bit>
    <bit pos="15">WDF detected a non-zero syndrome (CE ore UE) from USTL</bit>
    <bit pos="16">WDF CMD parity errror</bit>
    <bit pos="17">Unused</bit>
    <bit pos="18">Unused</bit>
    <bit pos="19">Read Buffers overflowed/underflowed (more than 64 in use)</bit>
    <bit pos="20">WRT CE detected on buffer output</bit>
    <bit pos="21">WRT UE detected on buffer output</bit>
    <bit pos="22">WRT SUE detected on buffer output</bit>
    <bit pos="23">WRT detected a scom sequencer error</bit>
    <bit pos="24">WRT detected a parity error on the misc_reg scom register</bit>
    <bit pos="25">WRT Data Syndrome not equal to 0 for input for write buffer</bit>
    <bit pos="26">No buffer error; Buffer manager parity error</bit>
    <bit pos="27">A fail response set as checkstop occurred for chana</bit>
    <bit pos="28">A fail response set as checkstop occurred for chanb</bit>
    <bit pos="29">A fail response set as recoverable occurred for chana</bit>
    <bit pos="30">A fail response set as recoverable occurred for chanb</bit>
    <bit pos="31">A lol drop set as checkstop occurred for chana</bit>
    <bit pos="32">A lol drop set as checkstop occurred for chanb</bit>
    <bit pos="33">A lol drop set as recoverable occurred for chana</bit>
    <bit pos="34">A lol drop set as recoverable occurred for chanb</bit>
    <bit pos="35">flit data pariry error from dl for chana</bit>
    <bit pos="36">flit data pariry error from dl for chanb</bit>
    <bit pos="37">internal fifo parity error for chana</bit>
    <bit pos="38">internal fifo parity error for chanb</bit>
    <bit pos="39">Unexpected read or write response received, chana</bit>
    <bit pos="40">Unexpected read or write response received, chanb</bit>
    <bit pos="41">Bad data set for data that is not valid chana</bit>
    <bit pos="42">Bad data set for data that is not valid chanb</bit>
    <bit pos="43">Memory read data returned in template 0, chana</bit>
    <bit pos="44">Memory read data returned in template 0, chanb</bit>
    <bit pos="45">Recieved mmio response while in LOL mode chana</bit>
    <bit pos="46">Recieved mmio response while in LOL mode chanb</bit>
    <bit pos="47">valid bad data or SUE received channel a</bit>
    <bit pos="48">Valid bad data or SUE received chanb</bit>
    <bit pos="49">ChanA excessive data error</bit>
    <bit pos="50">ChanB excessive data error</bit>
    <bit pos="51">Commit state where commit data is not marked as valid</bit>
    <bit pos="52">Commit state where commit data is not marked as valid</bit>
    <bit pos="53">A fifo in the ustl chana overflowed</bit>
    <bit pos="54">A fifo in the ustl chanb overflowed</bit>
    <bit pos="55">Invalid command decoded in USTL FF subchannel A</bit>
    <bit pos="56">Invalid command decoded in USTL FF subchannel B</bit>
    <bit pos="57">Fatal register parity error</bit>
    <bit pos="58">recov register parity error</bit>
    <bit pos="59">ChanA response invalid(dlength and/or dpart received)</bit>
    <bit pos="60">ChanB response invalid(dlength and/or dpart received)</bit>
    <bit pos="61">spare</bit>
</attn_node>