Zane Shelley | c928f94 | 2021-07-09 14:32:58 -0500 | [diff] [blame] | 1 | <?xml version="1.0" encoding="UTF-8"?> |
| 2 | <attn_node model_ec="EXPLORER_11,EXPLORER_20" name="OMI_DL" reg_type="SCOM"> |
| 3 | |
| 4 | <register name="OMI_DL_CONFIG0"> |
| 5 | <instance reg_inst="0" addr="0x08012810" /> |
| 6 | </register> |
| 7 | |
| 8 | <register name="OMI_DL_CONFIG1"> |
| 9 | <instance reg_inst="0" addr="0x08012811" /> |
| 10 | </register> |
| 11 | |
| 12 | <register name="OMI_DL_ERR_MASK"> |
| 13 | <instance reg_inst="0" addr="0x08012812" /> |
| 14 | </register> |
| 15 | |
| 16 | <register name="OMI_DL_ERR_RPT"> |
| 17 | <instance reg_inst="0" addr="0x08012813" /> |
| 18 | </register> |
| 19 | |
| 20 | <register name="OMI_DL_ERR_CAPTURE"> |
| 21 | <instance reg_inst="0" addr="0x08012814" /> |
| 22 | </register> |
| 23 | |
| 24 | <register name="OMI_DL_EDPL_MAX_COUNT"> |
| 25 | <instance reg_inst="0" addr="0x08012815" /> |
| 26 | </register> |
| 27 | |
| 28 | <register name="OMI_DL_STATUS"> |
| 29 | <instance reg_inst="0" addr="0x08012816" /> |
| 30 | </register> |
| 31 | |
| 32 | <register name="OMI_DL_TRAINING_STATUS"> |
| 33 | <instance reg_inst="0" addr="0x08012817" /> |
| 34 | </register> |
| 35 | |
| 36 | <register name="OMI_DL_DLX_CONFIG"> |
| 37 | <instance reg_inst="0" addr="0x08012818" /> |
| 38 | </register> |
| 39 | |
| 40 | <register name="OMI_DL_DLX_INFO"> |
| 41 | <instance reg_inst="0" addr="0x08012819" /> |
| 42 | </register> |
| 43 | |
| 44 | <register name="OMI_DL_ERR_ACTION"> |
| 45 | <instance reg_inst="0" addr="0x0801281D" /> |
| 46 | </register> |
| 47 | |
| 48 | <register name="OMI_DL_DEBUG_AID"> |
| 49 | <instance reg_inst="0" addr="0x0801281E" /> |
| 50 | </register> |
| 51 | |
| 52 | <register name="OMI_DL_CYA_BITS"> |
| 53 | <instance reg_inst="0" addr="0x0801281F" /> |
| 54 | </register> |
| 55 | |
| 56 | <capture_group node_inst="0"> |
| 57 | <capture_register reg_name="OMI_DL_CONFIG0" reg_inst="0" /> |
| 58 | <capture_register reg_name="OMI_DL_CONFIG1" reg_inst="0" /> |
| 59 | <capture_register reg_name="OMI_DL_ERR_MASK" reg_inst="0" /> |
| 60 | <capture_register reg_name="OMI_DL_ERR_RPT" reg_inst="0" /> |
| 61 | <capture_register reg_name="OMI_DL_ERR_CAPTURE" reg_inst="0" /> |
| 62 | <capture_register reg_name="OMI_DL_EDPL_MAX_COUNT" reg_inst="0" /> |
| 63 | <capture_register reg_name="OMI_DL_STATUS" reg_inst="0" /> |
| 64 | <capture_register reg_name="OMI_DL_TRAINING_STATUS" reg_inst="0" /> |
| 65 | <capture_register reg_name="OMI_DL_DLX_CONFIG" reg_inst="0" /> |
| 66 | <capture_register reg_name="OMI_DL_DLX_INFO" reg_inst="0" /> |
| 67 | <capture_register reg_name="OMI_DL_ERR_ACTION" reg_inst="0" /> |
| 68 | <capture_register reg_name="OMI_DL_DEBUG_AID" reg_inst="0" /> |
| 69 | <capture_register reg_name="OMI_DL_CYA_BITS" reg_inst="0" /> |
| 70 | </capture_group> |
| 71 | |
| 72 | <rule attn_type="UCS" node_inst="0"> |
| 73 | <!-- FIR & ~MASK & ~ACT0 & ~ACT1 & 0xfffff00000000000--> |
| 74 | <expr type="and"> |
| 75 | <expr type="reg" value1="OMI_DL_FIR"/> |
| 76 | <expr type="not"> |
| 77 | <expr type="reg" value1="OMI_DL_FIR_MASK"/> |
| 78 | </expr> |
| 79 | <expr type="not"> |
| 80 | <expr type="reg" value1="OMI_DL_FIR_ACT0"/> |
| 81 | </expr> |
| 82 | <expr type="not"> |
| 83 | <expr type="reg" value1="OMI_DL_FIR_ACT1"/> |
| 84 | </expr> |
| 85 | <expr type="int" value1="0xfffff00000000000" /> |
| 86 | </expr> |
| 87 | </rule> |
| 88 | |
| 89 | <rule attn_type="RE" node_inst="0"> |
| 90 | <!-- FIR & ~MASK & ~ACT0 & ACT1 & 0xfffff00000000000--> |
| 91 | <expr type="and"> |
| 92 | <expr type="reg" value1="OMI_DL_FIR"/> |
| 93 | <expr type="not"> |
| 94 | <expr type="reg" value1="OMI_DL_FIR_MASK"/> |
| 95 | </expr> |
| 96 | <expr type="not"> |
| 97 | <expr type="reg" value1="OMI_DL_FIR_ACT0"/> |
| 98 | </expr> |
| 99 | <expr type="reg" value1="OMI_DL_FIR_ACT1"/> |
| 100 | <expr type="int" value1="0xfffff00000000000" /> |
| 101 | </expr> |
| 102 | </rule> |
| 103 | |
| 104 | <rule attn_type="HA" node_inst="0"> |
| 105 | <!-- FIR & ~MASK & ACT0 & ~ACT1 & 0xfffff00000000000--> |
| 106 | <expr type="and"> |
| 107 | <expr type="reg" value1="OMI_DL_FIR"/> |
| 108 | <expr type="not"> |
| 109 | <expr type="reg" value1="OMI_DL_FIR_MASK"/> |
| 110 | </expr> |
| 111 | <expr type="reg" value1="OMI_DL_FIR_ACT0"/> |
| 112 | <expr type="not"> |
| 113 | <expr type="reg" value1="OMI_DL_FIR_ACT1"/> |
| 114 | </expr> |
| 115 | <expr type="int" value1="0xfffff00000000000" /> |
| 116 | </expr> |
| 117 | </rule> |
| 118 | |
| 119 | <bit pos= "0" child_node="OMI_DL_ERR_RPT" node_inst="0">OMI-DL fatal error</bit> |
| 120 | <bit pos= "1">OMI-DL UE on data flit</bit> |
| 121 | <bit pos= "2">OMI-DL CE on TL flit</bit> |
| 122 | <bit pos= "3">OMI-DL detected a CRC error</bit> |
| 123 | <bit pos= "4">OMI-DL received a nack</bit> |
| 124 | <bit pos= "5">OMI-DL running in degraded mode</bit> |
| 125 | <bit pos= "6">OMI-DL parity error detection on a lane</bit> |
| 126 | <bit pos= "7">OMI-DL retrained due to no forward progress</bit> |
| 127 | <bit pos= "8">OMI-DL remote side initiated a retrain</bit> |
| 128 | <bit pos= "9">OMI-DL retrain due to internal error or software</bit> |
| 129 | <bit pos="10">OMI-DL threshold reached</bit> |
| 130 | <bit pos="11">OMI-DL trained</bit> |
| 131 | <bit pos="12">OMI-DL endpoint error bit 0</bit> |
| 132 | <bit pos="13">OMI-DL endpoint error bit 1</bit> |
| 133 | <bit pos="14">OMI-DL endpoint error bit 2</bit> |
| 134 | <bit pos="15">OMI-DL endpoint error bit 3</bit> |
| 135 | <bit pos="16">OMI-DL endpoint error bit 4</bit> |
| 136 | <bit pos="17">OMI-DL endpoint error bit 5</bit> |
| 137 | <bit pos="18">OMI-DL endpoint error bit 6</bit> |
| 138 | <bit pos="19">OMI-DL endpoint error bit 7</bit> |
| 139 | |
| 140 | </attn_node> |