xml/p10/node_occ_fir.xml

<?xml version="1.0" encoding="UTF-8"?>
<attn_node model_ec="P10_10,P10_20" name="OCC_FIR" reg_type="SCOM">
    <local_fir config="" name="OCC_FIR">
        <instance addr="0x01010800" reg_inst="0"/>
        <action attn_type="CS" config="00"/>
        <action attn_type="RE" config="01"/>
    </local_fir>
    <register name="OCC_SCOM_ERR_RPT">
        <instance addr="0x0101080A" reg_inst="0"/>
    </register>
    <register name="OCC_SCOM_ERR_RPT2">
        <instance addr="0x0101080B" reg_inst="0"/>
    </register>
    <capture_group node_inst="0">
        <capture_register reg_inst="0" reg_name="OCC_SCOM_ERR_RPT" />
        <capture_register reg_inst="0" reg_name="OCC_SCOM_ERR_RPT2" />
    </capture_group>
    <bit pos="0">OCC_FW0</bit>
    <bit pos="1">OCC_FW1</bit>
    <bit pos="2">OCC_QME_ERROR_NOTIFY</bit>
    <bit pos="3">reserved</bit>
    <bit pos="4">OCC Heartbeat Error</bit>
    <bit pos="5">GPE0 asserted a watchdog timeout condition</bit>
    <bit pos="6">GPE1 asserted a watchdog timeout condition</bit>
    <bit pos="7">GPE2 asserted a watchdog timeout condition</bit>
    <bit pos="8">GPE3 asserted a watchdog timeout condition</bit>
    <bit pos="9">GPE0 asserted an error condition that caused it to halt.</bit>
    <bit pos="10">GPE1 asserted an error condition that caused it to halt.</bit>
    <bit pos="11">GPE2 asserted an error condition that caused it to halt.</bit>
    <bit pos="12">GPE3 asserted an error condition that caused it to halt.</bit>
    <bit pos="13">OCB Error to PM Hcode for PM Complex Restart</bit>
    <bit pos="14">SRAM UE to PM Hcode for PM Complex Restart</bit>
    <bit pos="15">SRAM CE</bit>
    <bit pos="16">GPE0 asserted a halt condition</bit>
    <bit pos="17">GPE1 asserted a halt condition</bit>
    <bit pos="18">GPE2 asserted a halt condition</bit>
    <bit pos="19">GPE3 asserted a halt condition</bit>
    <bit pos="20">GPE0 attempted to write outside the region defined in GPESWPR</bit>
    <bit pos="21">GPE1 attempted to write outside the region defined in GPESWPR</bit>
    <bit pos="22">GPE2 attempted to write outside the region defined in GPESWPR</bit>
    <bit pos="23">GPE3 attempted to write outside the region defined in GPESWPR</bit>
    <bit pos="24">Safe Mode for debug use</bit>
    <bit pos="25">reserved</bit>
    <bit pos="26">EXTERNAL_TRAP</bit>
    <bit pos="27">PPC405 Core Reset Output asserted (OCC firmware)</bit>
    <bit pos="28">PPC405 Chip Reset Output asserted (OCC firmware)</bit>
    <bit pos="29">PPC405 System Reset Output asserted (OCC firmware)</bit>
    <bit pos="30">PPC405 Wait State asserted (OCC firmware)</bit>
    <bit pos="31">PPC405 Stop Ack output asserted</bit>
    <bit pos="32">OCB Direct Bridge Error</bit>
    <bit pos="33">OCB PIB Address Parity Error</bit>
    <bit pos="34">Indirect Channel Error</bit>
    <bit pos="35">Parity error detected on OPIT interrupt bus</bit>
    <bit pos="36">OPIT interrupt state machine error occurred</bit>
    <bit pos="37">reserved</bit>
    <bit pos="38">reserved</bit>
    <bit pos="39">reserved</bit>
    <bit pos="40">reserved</bit>
    <bit pos="41">reserved</bit>
    <bit pos="42">JTAG accelerator error</bit>
    <bit pos="43">Any OCI Slave error occurreds</bit>
    <bit pos="44">PPC405 cache UE</bit>
    <bit pos="45">PPC405 cache CE</bit>
    <bit pos="46">PPC405 Machine Check</bit>
    <bit pos="47">SRAM spare direct error Summary</bit>
    <bit pos="48">Read, write, or parity error in the SRAM tank controller</bit>
    <bit pos="49">reserved</bit>
    <bit pos="50">reserved</bit>
    <bit pos="51">OCI slave error for GPE0</bit>
    <bit pos="52">OCI slave error for GPE1</bit>
    <bit pos="53">OCI slave error for GPE2</bit>
    <bit pos="54">OCI slave error for GPE3</bit>
    <bit pos="55">PPC405 ICU timeout on OCI request</bit>
    <bit pos="56">PPC405 DCU timeout on OCI request</bit>
    <bit pos="57">OCC fault occurred (to achieve safe mode)</bit>
    <bit pos="58">Read by HYP as part of the communication of a Power Management fault</bit>
    <bit pos="59">reserved</bit>
    <bit pos="60">reserved</bit>
    <bit pos="61">reserved</bit>
</attn_node>