| Zane Shelley | abc51c2 | 2020-11-09 21:35:35 -0600 | [diff] [blame] | 1 | <?xml version="1.0" encoding="UTF-8"?> |
| Zane Shelley | f8a726b | 2020-12-16 21:29:32 -0600 | [diff] [blame^] | 2 | <attn_node model_ec="P10_10,P10_20" name="GFIR_SPA" reg_type="SCOM"> |
| Zane Shelley | abc51c2 | 2020-11-09 21:35:35 -0600 | [diff] [blame] | 3 | <register name="GFIR_REG_SPA"> |
| 4 | <instance addr="0x570F001A" reg_inst="0"/> |
| 5 | </register> |
| 6 | <rule attn_type="SPA" node_inst="0"> |
| 7 | <expr type="reg" value1="GFIR_REG_SPA"/> |
| 8 | </rule> |
| 9 | <bit child_node="CFIR_TP_SPA_UCS_HA" node_inst="0" pos="1">XSTOP Register - after masking - OLD XFIR</bit> |
| 10 | <bit child_node="CFIR_N0_SPA" node_inst="0" pos="2">XSTOP Register - after masking - OLD XFIR</bit> |
| 11 | <bit child_node="CFIR_N1_SPA" node_inst="0" pos="3">XSTOP Register - after masking - OLD XFIR</bit> |
| 12 | <bit child_node="CFIR_PCI_SPA_HA" node_inst="0" pos="8">XSTOP Register - after masking - OLD XFIR</bit> |
| 13 | <bit child_node="CFIR_PCI_SPA_HA" node_inst="1" pos="9">XSTOP Register - after masking - OLD XFIR</bit> |
| 14 | <bit child_node="CFIR_MC_CS_RE_SPA" node_inst="0" pos="12">XSTOP Register - after masking - OLD XFIR</bit> |
| 15 | <bit child_node="CFIR_MC_CS_RE_SPA" node_inst="1" pos="13">XSTOP Register - after masking - OLD XFIR</bit> |
| 16 | <bit child_node="CFIR_MC_CS_RE_SPA" node_inst="2" pos="14">XSTOP Register - after masking - OLD XFIR</bit> |
| 17 | <bit child_node="CFIR_MC_CS_RE_SPA" node_inst="3" pos="15">XSTOP Register - after masking - OLD XFIR</bit> |
| 18 | <bit child_node="CFIR_PAUE_SPA" node_inst="0" pos="16">XSTOP Register - after masking - OLD XFIR</bit> |
| 19 | <bit child_node="CFIR_PAUE_SPA" node_inst="1" pos="17">XSTOP Register - after masking - OLD XFIR</bit> |
| 20 | <bit child_node="CFIR_PAUW_SPA" node_inst="0" pos="18">XSTOP Register - after masking - OLD XFIR</bit> |
| 21 | <bit child_node="CFIR_PAUW_SPA" node_inst="1" pos="19">XSTOP Register - after masking - OLD XFIR</bit> |
| 22 | <bit child_node="CFIR_IOHS_CS_RE_SPA" node_inst="0" pos="24">XSTOP Register - after masking - OLD XFIR</bit> |
| 23 | <bit child_node="CFIR_IOHS_CS_RE_SPA" node_inst="1" pos="25">XSTOP Register - after masking - OLD XFIR</bit> |
| 24 | <bit child_node="CFIR_IOHS_CS_RE_SPA" node_inst="2" pos="26">XSTOP Register - after masking - OLD XFIR</bit> |
| 25 | <bit child_node="CFIR_IOHS_CS_RE_SPA" node_inst="3" pos="27">XSTOP Register - after masking - OLD XFIR</bit> |
| 26 | <bit child_node="CFIR_IOHS_CS_RE_SPA" node_inst="4" pos="28">XSTOP Register - after masking - OLD XFIR</bit> |
| 27 | <bit child_node="CFIR_IOHS_CS_RE_SPA" node_inst="5" pos="29">XSTOP Register - after masking - OLD XFIR</bit> |
| 28 | <bit child_node="CFIR_IOHS_CS_RE_SPA" node_inst="6" pos="30">XSTOP Register - after masking - OLD XFIR</bit> |
| 29 | <bit child_node="CFIR_IOHS_CS_RE_SPA" node_inst="7" pos="31">XSTOP Register - after masking - OLD XFIR</bit> |
| 30 | <bit child_node="CFIR_EQ_SPA" node_inst="0" pos="32">XSTOP Register - after masking - OLD XFIR</bit> |
| 31 | <bit child_node="CFIR_EQ_SPA" node_inst="1" pos="33">XSTOP Register - after masking - OLD XFIR</bit> |
| 32 | <bit child_node="CFIR_EQ_SPA" node_inst="2" pos="34">XSTOP Register - after masking - OLD XFIR</bit> |
| 33 | <bit child_node="CFIR_EQ_SPA" node_inst="3" pos="35">XSTOP Register - after masking - OLD XFIR</bit> |
| 34 | <bit child_node="CFIR_EQ_SPA" node_inst="4" pos="36">XSTOP Register - after masking - OLD XFIR</bit> |
| 35 | <bit child_node="CFIR_EQ_SPA" node_inst="5" pos="37">XSTOP Register - after masking - OLD XFIR</bit> |
| 36 | <bit child_node="CFIR_EQ_SPA" node_inst="6" pos="38">XSTOP Register - after masking - OLD XFIR</bit> |
| 37 | <bit child_node="CFIR_EQ_SPA" node_inst="7" pos="39">XSTOP Register - after masking - OLD XFIR</bit> |
| 38 | </attn_node> |