Zane Shelley | abc51c2 | 2020-11-09 21:35:35 -0600 | [diff] [blame] | 1 | <?xml version="1.0" encoding="UTF-8"?> |
Zane Shelley | f8a726b | 2020-12-16 21:29:32 -0600 | [diff] [blame] | 2 | <attn_node model_ec="P10_10,P10_20" name="CFIR_PCI_CS_RE" reg_type="SCOM"> |
Zane Shelley | abc51c2 | 2020-11-09 21:35:35 -0600 | [diff] [blame] | 3 | <register name="CFIR_PCI_XSTOP"> |
| 4 | <instance addr="0x08040000" reg_inst="0"/> |
| 5 | <instance addr="0x09040000" reg_inst="1"/> |
| 6 | </register> |
| 7 | <register name="CFIR_PCI_XSTOP_MASK"> |
| 8 | <instance addr="0x08040040" reg_inst="0"/> |
| 9 | <instance addr="0x09040040" reg_inst="1"/> |
| 10 | </register> |
| 11 | <register name="CFIR_PCI_RECOV"> |
| 12 | <instance addr="0x08040001" reg_inst="0"/> |
| 13 | <instance addr="0x09040001" reg_inst="1"/> |
| 14 | </register> |
| 15 | <register name="CFIR_PCI_RECOV_MASK"> |
| 16 | <instance addr="0x08040041" reg_inst="0"/> |
| 17 | <instance addr="0x09040041" reg_inst="1"/> |
| 18 | </register> |
| 19 | <rule attn_type="CS" node_inst="0:1"> |
| 20 | <expr type="and"> |
| 21 | <expr type="reg" value1="CFIR_PCI_XSTOP"/> |
| 22 | <expr type="not"> |
| 23 | <expr type="reg" value1="CFIR_PCI_XSTOP_MASK"/> |
| 24 | </expr> |
| 25 | <expr type="int" value1="0x0FFFFFFFFFFFFFFF"/> |
| 26 | </expr> |
| 27 | </rule> |
| 28 | <rule attn_type="RE" node_inst="0:1"> |
| 29 | <expr type="and"> |
| 30 | <expr type="reg" value1="CFIR_PCI_RECOV"/> |
| 31 | <expr type="not"> |
| 32 | <expr type="reg" value1="CFIR_PCI_RECOV_MASK"/> |
| 33 | </expr> |
| 34 | <expr type="int" value1="0x0FFFFFFFFFFFFFFF"/> |
| 35 | </expr> |
| 36 | </rule> |
| 37 | <bit child_node="PCI_LOCAL_FIR" node_inst="0,1" pos="4">Local FIR</bit> |
| 38 | <bit child_node="PCI_ETU_FIR" node_inst="0,3" pos="5">ETU FIR Register</bit> |
| 39 | <bit child_node="PCI_ETU_FIR" node_inst="1,4" pos="6">ETU FIR Register</bit> |
| 40 | <bit child_node="PCI_ETU_FIR" node_inst="2,5" pos="7">ETU FIR Register</bit> |
| 41 | <bit child_node="PCI_FIR" node_inst="0,3" pos="9">PCI FIR Register</bit> |
| 42 | <bit child_node="PCI_FIR" node_inst="1,4" pos="10">PCI FIR Register</bit> |
| 43 | <bit child_node="PCI_FIR" node_inst="2,5" pos="11">PCI FIR Register</bit> |
| 44 | <bit child_node="PCI_IOP_FIR" node_inst="0,2" pos="12">IOP Local Fault Isolation Register. Register bits are set for any error condition detected by the IOP. The IOPFIR will freeze upon logging the first error not masked in IOPMASK.</bit> |
| 45 | <bit child_node="PCI_IOP_FIR" node_inst="1,3" pos="13">IOP Local Fault Isolation Register. Register bits are set for any error condition detected by the IOP. The IOPFIR will freeze upon logging the first error not masked in IOPMASK.</bit> |
| 46 | </attn_node> |