Brad Bishop | a948d26 | 2016-10-05 19:51:48 -0400 | [diff] [blame] | 1 | description: > |
| 2 | Implement to provide CPU attributes. |
Cheng C Yang | 259f49e | 2020-02-25 10:07:32 +0800 | [diff] [blame] | 3 | properties: |
| 4 | - name: Socket |
| 5 | type: string |
| 6 | description: > |
| 7 | Processor Socket designation on MotherBoard. |
Brad Bishop | 6258c4f | 2022-09-14 10:53:57 -0400 | [diff] [blame] | 8 | default: "" |
Cheng C Yang | 259f49e | 2020-02-25 10:07:32 +0800 | [diff] [blame] | 9 | - name: Family |
| 10 | type: string |
| 11 | description: > |
Patrick Williams | a134741 | 2022-12-06 10:56:22 -0600 | [diff] [blame] | 12 | A free form string indicates processor family type. For example, |
| 13 | values can be "Intel Xeon processor", "AS400 Family", etc. |
Brad Bishop | a1a46a9 | 2022-09-14 10:56:01 -0400 | [diff] [blame] | 14 | default: "" |
Brandon Kim | 8d3d5a2 | 2021-10-06 12:51:31 -0700 | [diff] [blame] | 15 | - name: EffectiveFamily |
| 16 | type: uint16 |
| 17 | description: > |
Patrick Williams | a134741 | 2022-12-06 10:56:22 -0600 | [diff] [blame] | 18 | The effective Family information as provided by the manufacturer of |
| 19 | this processor in unsigned integer. Default set to 0x02 which is |
| 20 | defined as "Unknown" Processor Family in DSP0134 section 7.5.2. |
Brandon Kim | 8d3d5a2 | 2021-10-06 12:51:31 -0700 | [diff] [blame] | 21 | default: 0x02 |
| 22 | - name: EffectiveModel |
| 23 | type: uint16 |
Brandon Kim | 40a42aa | 2021-09-09 19:17:04 -0700 | [diff] [blame] | 24 | description: > |
Patrick Williams | a134741 | 2022-12-06 10:56:22 -0600 | [diff] [blame] | 25 | The effective Model information as provided by the manufacturer of |
| 26 | this processor in unsigned integer. |
Brandon Kim | 8d3d5a2 | 2021-10-06 12:51:31 -0700 | [diff] [blame] | 27 | default: 0 |
Cheng C Yang | 259f49e | 2020-02-25 10:07:32 +0800 | [diff] [blame] | 28 | - name: Id |
| 29 | type: uint64 |
| 30 | description: > |
Patrick Williams | a134741 | 2022-12-06 10:56:22 -0600 | [diff] [blame] | 31 | This Processor ID field contains processor-specific information that |
| 32 | describes the processor's features. Details depend on processor |
| 33 | architecture. For x86 and ARM processors, DMTF DSP0134 Section 7.5.3 |
| 34 | is used. |
Cheng C Yang | 259f49e | 2020-02-25 10:07:32 +0800 | [diff] [blame] | 35 | default: 0 |
| 36 | - name: MaxSpeedInMhz |
| 37 | type: uint32 |
| 38 | description: > |
| 39 | Max Speed in megahertz the CPU can support. |
| 40 | - name: Characteristics |
| 41 | type: array[enum[self.Capability]] |
| 42 | description: > |
Patrick Williams | a134741 | 2022-12-06 10:56:22 -0600 | [diff] [blame] | 43 | The set of boolean flags for processor's capability, such as 64-bit |
| 44 | Capable, Multi-Core, Hardware Thread, Execute Protection, Enhanced |
| 45 | Virtualization, Power/Performance Control etc. |
Cheng C Yang | 259f49e | 2020-02-25 10:07:32 +0800 | [diff] [blame] | 46 | - name: CoreCount |
| 47 | type: uint16 |
| 48 | description: > |
| 49 | The number of cores in the processor. |
| 50 | - name: ThreadCount |
| 51 | type: uint16 |
| 52 | description: > |
| 53 | The maximum number of threads the processor can support. |
Brandon Kim | d81cff3 | 2021-09-01 10:00:13 -0700 | [diff] [blame] | 54 | - name: Step |
Brandon Kim | 0170a76 | 2021-10-19 18:51:14 -0700 | [diff] [blame] | 55 | type: uint16 |
Brandon Kim | d81cff3 | 2021-09-01 10:00:13 -0700 | [diff] [blame] | 56 | description: > |
| 57 | The step value for this processor |
Michael Shen | 2ff1081 | 2023-02-13 01:47:11 +0000 | [diff] [blame] | 58 | default: maxint |
Brandon Kim | d81cff3 | 2021-09-01 10:00:13 -0700 | [diff] [blame] | 59 | - name: Microcode |
Brandon Kim | 0170a76 | 2021-10-19 18:51:14 -0700 | [diff] [blame] | 60 | type: uint32 |
Brandon Kim | d81cff3 | 2021-09-01 10:00:13 -0700 | [diff] [blame] | 61 | description: > |
| 62 | The microcode information for this processor |
Brandon Kim | 0170a76 | 2021-10-19 18:51:14 -0700 | [diff] [blame] | 63 | default: 0 |
Cheng C Yang | 259f49e | 2020-02-25 10:07:32 +0800 | [diff] [blame] | 64 | |
| 65 | enumerations: |
| 66 | - name: Capability |
| 67 | description: > |
Patrick Williams | a134741 | 2022-12-06 10:56:22 -0600 | [diff] [blame] | 68 | List of capabilities that a processor can support. Values are based |
| 69 | off DMTF DSP0134 specification. |
Cheng C Yang | 259f49e | 2020-02-25 10:07:32 +0800 | [diff] [blame] | 70 | values: |
Patrick Williams | 8da396c | 2022-03-14 14:21:02 -0500 | [diff] [blame] | 71 | - name: Capable64bit |
| 72 | description: > |
| 73 | Capable of 64-bit. |
| 74 | - name: MultiCore |
| 75 | description: > |
| 76 | Support multi-core. |
| 77 | - name: HardwareThread |
| 78 | description: > |
| 79 | Support hardware thread. |
| 80 | - name: ExecuteProtection |
| 81 | description: > |
| 82 | Support execute protection. |
| 83 | - name: EnhancedVirtualization |
| 84 | description: > |
| 85 | Support enhanced virtualization. |
| 86 | - name: PowerPerformanceControl |
| 87 | description: > |
| 88 | Support power/performance control. |
Brad Bishop | df55704 | 2021-10-04 15:51:11 -0400 | [diff] [blame] | 89 | |
| 90 | associations: |
| 91 | - name: associated_pcie_slots |
| 92 | description: > |
| 93 | Objects that implement Cpu can optionally implement the |
| 94 | associated_pcie_slots association to provide a link to one or more |
| 95 | PCIe slots. |
Zhenwei Chen | 453957c | 2022-03-31 17:54:17 -0700 | [diff] [blame] | 96 | reverse_names: |
| 97 | - upstream_processor |
Brad Bishop | df55704 | 2021-10-04 15:51:11 -0400 | [diff] [blame] | 98 | required_endpoint_interfaces: |
Patrick Williams | 8da396c | 2022-03-14 14:21:02 -0500 | [diff] [blame] | 99 | - xyz.openbmc_project.Inventory.Item.PCIeSlot |