Gitiles
Code Review Sign In
gerrit.openbmc.org / openbmc / phosphor-power / b59b1fa2bb80ec968a706189b380a0cf6e4482a0 / . / phosphor-regulators / config_files / Rainier.json
blob: 09c005febad8e046c37a91dd93381f330fafb575 [file] [log] [blame]
Shawn McCarney46b5e692020-04-30 16:34:39 -0500[diff] [blame]1{
Patrick Williams0dbce562022-12-12 10:43:31 -0600[diff] [blame]2 "comments": [
3 "phosphor-regulators configuration file for IBM Rainier systems"
4 ],
Shawn McCarney46b5e692020-04-30 16:34:39 -0500[diff] [blame]5
Patrick Williams0dbce562022-12-12 10:43:31 -0600[diff] [blame]6 "rules": [
Shawn McCarney46b5e692020-04-30 16:34:39 -0500[diff] [blame]7 {
Patrick Williams0dbce562022-12-12 10:43:31 -0600[diff] [blame]8 "comments": ["Rule to set PMBus PAGE to 0"],
9 "id": "set_page0_rule",
10 "actions": [
11 { "i2c_write_byte": { "register": "0x00", "value": "0x00" } }
12 ]
13 },
14
15 {
16 "comments": ["Rule to set PMBus PAGE to 1"],
17 "id": "set_page1_rule",
18 "actions": [
19 { "i2c_write_byte": { "register": "0x00", "value": "0x01" } }
20 ]
21 },
22
23 {
24 "comments": ["Rule to set output voltage of a PMBus regulator"],
25 "id": "set_voltage_rule",
26 "actions": [
27 {
28 "comments": [
29 "Write volts value to VOUT_COMMAND in linear format.",
Shawn McCarney46b5e692020-04-30 16:34:39 -0500[diff] [blame]30 "Get volts value from configuration. Get exponent",
Patrick Williams0dbce562022-12-12 10:43:31 -0600[diff] [blame]31 "from VOUT_MODE. Verify write was successful."
32 ],
33 "pmbus_write_vout_command": {
34 "format": "linear",
35 "is_verified": true
36 }
37 }
38 ]
Shawn McCarneyd97aa512022-03-24 19:02:32 -0500[diff] [blame]39 },
40
41 {
Patrick Williams0dbce562022-12-12 10:43:31 -0600[diff] [blame]42 "comments": [
43 "Rule to set output voltage of PAGE 0 of a PMBus regulator"
44 ],
45 "id": "set_voltage_page0_rule",
46 "actions": [
47 { "run_rule": "set_page0_rule" },
48 { "run_rule": "set_voltage_rule" }
49 ]
Shawn McCarneyd97aa512022-03-24 19:02:32 -0500[diff] [blame]50 },
51
52 {
Patrick Williams0dbce562022-12-12 10:43:31 -0600[diff] [blame]53 "comments": [
54 "Rule to set output voltage of PAGE 1 of a PMBus regulator"
55 ],
56 "id": "set_voltage_page1_rule",
57 "actions": [
58 { "run_rule": "set_page1_rule" },
59 { "run_rule": "set_voltage_rule" }
60 ]
61 },
62
63 {
64 "comments": [
65 "Rule to set output voltage of a PMBus regulator using",
66 "PMBus OPERATION and VOUT_COMMAND"
67 ],
68 "id": "set_operation_and_voltage_rule",
69 "actions": [
70 {
71 "comments": [
72 "Set PMBus OPERATION to 0x80 indicating output voltage",
73 "is set by the PMBus VOUT_COMMAND"
74 ],
75 "i2c_write_byte": { "register": "0x01", "value": "0x80" }
76 },
77
78 {
79 "comments": [
80 "Set the output voltage using the PMBus VOUT_COMMAND"
81 ],
82 "run_rule": "set_voltage_rule"
83 },
84
85 {
86 "comments": [
87 "Set PMBus OPERATION to 0xB0 indicating output voltage",
Shawn McCarneyd97aa512022-03-24 19:02:32 -0500[diff] [blame]88 "will now be set by AVSBus (AVS_VOUT_COMMAND).",
89 "Hardware settings cause the VOUT_COMMAND value to be",
Patrick Williams0dbce562022-12-12 10:43:31 -0600[diff] [blame]90 "the initial voltage value for AVSBus."
91 ],
92 "i2c_write_byte": { "register": "0x01", "value": "0xB0" }
93 }
94 ]
95 },
Shawn McCarneyd97aa512022-03-24 19:02:32 -0500[diff] [blame]96
Shawn McCarneyd97aa512022-03-24 19:02:32 -0500[diff] [blame]97 {
Patrick Williams0dbce562022-12-12 10:43:31 -0600[diff] [blame]98 "comments": [
99 "Rule to set IOUT_OC_WARN_LIMIT for a PMBus regulator"
100 ],
101 "id": "set_iout_oc_warn_limit_rule",
102 "actions": [
103 {
104 "comments": [
105 "Set PMBus IOUT_OC_WARN_LIMIT to 326A to ensure OCW",
Shawn McCarneyd97aa512022-03-24 19:02:32 -0500[diff] [blame]106 "asserts at the roll-over bug identified in the",
107 "silicon. 326A = 0x08A3. PMBus requires",
Patrick Williams0dbce562022-12-12 10:43:31 -0600[diff] [blame]108 "the low order byte to be written first."
109 ],
110 "i2c_write_bytes": {
111 "register": "0x4A",
112 "values": ["0xA3", "0x08"]
113 }
114 }
Shawn McCarneyd97aa512022-03-24 19:02:32 -0500[diff] [blame]115 ]
Patrick Williams0dbce562022-12-12 10:43:31 -0600[diff] [blame]116 },
Shawn McCarneyd97aa512022-03-24 19:02:32 -0500[diff] [blame]117
Shawn McCarneyd97aa512022-03-24 19:02:32 -0500[diff] [blame]118 {
Patrick Williams0dbce562022-12-12 10:43:31 -0600[diff] [blame]119 "comments": [
120 "Rule to configure a VDD rail using the PMBus interface"
121 ],
122 "id": "configure_vdd_rule",
123 "actions": [
124 { "run_rule": "set_page0_rule" },
125 { "run_rule": "set_iout_oc_warn_limit_rule" },
126 {
127 "comments": [
128 "Set VOUT_MODE to exponent of -9 for VDD regulator",
129 "to support older and newer hardware."
130 ],
131 "i2c_write_byte": { "register": "0x20", "value": "0x17" }
132 },
133 { "run_rule": "set_operation_and_voltage_rule" },
134 {
135 "comments": [
136 "Set VOUT_MIN to 0V since for VDD the voltage",
137 "can go down to 0.5V so we want to lower this",
138 "limit below 0.5V so the regulator does not trip."
139 ],
140 "i2c_write_bytes": {
141 "register": "0x2B",
142 "values": ["0x00", "0x00"]
143 }
144 },
145 {
146 "comments": [
147 "Set VOUT_MAX to 1.255V since for VDD the voltage",
148 "can go up to 1.1V so we want to raise this",
149 "limit above 1.1V so the regulator does not trip."
150 ],
151 "i2c_write_bytes": {
152 "register": "0x24",
153 "values": ["0x83", "0x02"]
154 }
155 },
156 {
157 "comments": [
158 "Set POWER_GOOD_ON for VDD to a value of 0.5V."
159 ],
160 "i2c_write_bytes": {
161 "register": "0x5E",
162 "values": ["0x00", "0x01"]
163 }
164 },
165 {
166 "comments": [
167 "Set POWER_GOOD_OFF for VDD to a value of 0.4V."
168 ],
169 "i2c_write_bytes": {
170 "register": "0x5F",
171 "values": ["0xCD", "0x00"]
172 }
173 },
174 {
175 "comments": [
176 "Set VOUT_OV_WARN_LIMIT for VDD to a value of 1.30V."
177 ],
178 "i2c_write_bytes": {
179 "register": "0x42",
180 "values": ["0x9A", "0x02"]
181 }
182 },
183 {
184 "comments": [
185 "Set VOUT_UV_WARN_LIMIT for VDD to a value of 0.45V."
186 ],
187 "i2c_write_bytes": {
188 "register": "0x43",
189 "values": ["0xE6", "0x00"]
190 }
191 },
192 {
193 "comments": [
194 "Set TOFF_FALL time for VDD to a value of 10ms."
195 ],
196 "i2c_write_bytes": {
197 "register": "0x65",
198 "values": ["0x28", "0xF0"]
199 }
200 },
201 {
202 "comments": [
203 "Set IOUT_OC_FAULT_RESPONSE for VDD to shutdown."
204 ],
205 "i2c_write_byte": { "register": "0x47", "value": "0xC0" }
206 }
207 ]
208 },
209
210 {
211 "comments": [
212 "Rule to configure a VDN rail using the PMBus interface"
213 ],
214 "id": "configure_vdn_rule",
215 "actions": [
216 { "run_rule": "set_page0_rule" },
217 { "run_rule": "set_operation_and_voltage_rule" },
218 {
219 "comments": [
220 "Set VOUT_MIN to 0V since for VDN the voltage",
221 "can go down to 0.6V so we want to lower this",
222 "limit below 0.6V so the regulator does not trip."
223 ],
224 "i2c_write_bytes": {
225 "register": "0x2B",
226 "values": ["0x00", "0x00"]
227 }
228 },
229 {
230 "comments": [
231 "Set VOUT_MAX to 1.1V since for VDN the voltage",
232 "can go up to 1.0V so we want to raise this",
233 "limit above 1.0V so the regulator does not trip."
234 ],
235 "i2c_write_bytes": {
236 "register": "0x24",
237 "values": ["0x33", "0x02"]
238 }
239 },
240 {
241 "comments": [
242 "Set POWER_GOOD_ON for VDN to a value of 0.45V."
243 ],
244 "i2c_write_bytes": {
245 "register": "0x5E",
246 "values": ["0xE6", "0x00"]
247 }
248 },
249 {
250 "comments": [
251 "Set POWER_GOOD_OFF for VDN to a value of 0.40V."
252 ],
253 "i2c_write_bytes": {
254 "register": "0x5F",
255 "values": ["0xCC", "0x00"]
256 }
257 }
258 ]
259 },
260
261 {
262 "comments": [
263 "Rule to configure a VCS rail using the PMBus interface"
264 ],
265 "id": "configure_vcs_rule",
266 "actions": [
267 { "run_rule": "set_page1_rule" },
268 { "run_rule": "set_operation_and_voltage_rule" },
269 {
270 "comments": [
271 "Set VOUT_MIN to 0V since for VCS the voltage",
272 "can go down to 0.7V so we want to lower this",
273 "limit below 0.7V so the regulator does not trip."
274 ],
275 "i2c_write_bytes": {
276 "register": "0x2B",
277 "values": ["0x00", "0x00"]
278 }
279 },
280 {
281 "comments": [
282 "Set VOUT_MAX to 1.2V since for VCS the voltage",
283 "can go up to 1.1V so we want to raise this",
284 "limit above 1.1V so the regulator does not trip."
285 ],
286 "i2c_write_bytes": {
287 "register": "0x24",
288 "values": ["0x66", "0x02"]
289 }
290 },
291 {
292 "comments": [
293 "Set POWER_GOOD_ON for VCS to a value of 0.55V."
294 ],
295 "i2c_write_bytes": {
296 "register": "0x5E",
297 "values": ["0x19", "0x01"]
298 }
299 },
300 {
301 "comments": [
302 "Set POWER_GOOD_OFF for VCS to a value of 0.50V."
303 ],
304 "i2c_write_bytes": {
305 "register": "0x5F",
306 "values": ["0x00", "0x01"]
307 }
308 }
309 ]
310 },
311
312 {
313 "comments": [
314 "Rule to configure a VIO rail using the PMBus interface"
315 ],
316 "id": "configure_vio_rule",
317 "actions": [
318 { "run_rule": "set_page0_rule" },
319 { "run_rule": "set_operation_and_voltage_rule" },
320 {
321 "comments": [
322 "Set VOUT_MIN to 0V since for VIO the voltage",
323 "can go down to 0.8V so we want to lower this",
324 "limit below 0.8V so the regulator does not trip."
325 ],
326 "i2c_write_bytes": {
327 "register": "0x2B",
328 "values": ["0x00", "0x00"]
329 }
330 },
331 {
332 "comments": [
333 "Set VOUT_MAX to 1.1V since for VIO the voltage",
334 "can go up to 1.0V so we want to raise this",
335 "limit above 1.0V so the regulator does not trip."
336 ],
337 "i2c_write_bytes": {
338 "register": "0x24",
339 "values": ["0x33", "0x02"]
340 }
341 },
342 {
343 "comments": [
344 "Set POWER_GOOD_ON for VIO to a value of 0.55V."
345 ],
346 "i2c_write_bytes": {
347 "register": "0x5E",
348 "values": ["0x19", "0x01"]
349 }
350 },
351 {
352 "comments": [
353 "Set POWER_GOOD_OFF for VIO to a value of 0.50V."
354 ],
355 "i2c_write_bytes": {
356 "register": "0x5F",
357 "values": ["0x00", "0x01"]
358 }
359 }
360 ]
361 },
362
363 {
364 "comments": [
365 "Rule to configure a VPCIE rail using the PMBus interface"
366 ],
367 "id": "configure_vpcie_rule",
368 "actions": [
369 { "run_rule": "set_page0_rule" },
370 { "run_rule": "set_voltage_rule" },
371 {
372 "comments": [
373 "Set VOUT_MIN to 0V since for VPCIE the voltage",
374 "can go down to 0.81V so we want to lower this",
375 "limit below 0.81V so the regulator does not trip."
376 ],
377 "i2c_write_bytes": {
378 "register": "0x2B",
379 "values": ["0x00", "0x00"]
380 }
381 },
382 {
383 "comments": [
384 "Set VOUT_MAX to 1.0V since for VPCIE the voltage",
385 "can go up to 0.91V so we want to raise this",
386 "limit above 0.91V so the regulator does not trip."
387 ],
388 "i2c_write_bytes": {
389 "register": "0x24",
390 "values": ["0x00", "0x02"]
391 }
392 },
393 {
394 "comments": [
395 "Set POWER_GOOD_ON for VPCIE to a value of 0.65V."
396 ],
397 "i2c_write_bytes": {
398 "register": "0x5E",
399 "values": ["0x4C", "0x01"]
400 }
401 },
402 {
403 "comments": [
404 "Set POWER_GOOD_OFF for VPCIE to a value of 0.60V."
405 ],
406 "i2c_write_bytes": {
407 "register": "0x5F",
408 "values": ["0x33", "0x01"]
409 }
410 }
411 ]
412 },
413
414 {
415 "comments": [
416 "Rule to read sensors on IR38064 regulators using the",
417 "PMBus interface"
418 ],
419 "id": "read_sensors_ir38064_rule",
420 "actions": [
421 {
422 "comments": ["Read output current from READ_IOUT"],
423 "pmbus_read_sensor": {
424 "type": "iout",
425 "command": "0x8C",
426 "format": "linear_11"
427 }
428 },
429 {
430 "comments": [
431 "Read highest output current from MFR_IOUT_PEAK"
432 ],
433 "pmbus_read_sensor": {
434 "type": "iout_peak",
435 "command": "0xDC",
436 "format": "linear_11"
437 }
438 },
439 {
440 "comments": ["Read output power from READ_POUT"],
441 "pmbus_read_sensor": {
442 "type": "pout",
443 "command": "0x96",
444 "format": "linear_11"
445 }
446 },
447 {
448 "comments": ["Read temperature from READ_TEMPERATURE"],
449 "pmbus_read_sensor": {
450 "type": "temperature",
451 "command": "0x8D",
452 "format": "linear_11"
453 }
454 },
455 {
456 "comments": [
457 "Read highest temperature from MFR_TEMPERATURE_PEAK"
458 ],
459 "pmbus_read_sensor": {
460 "type": "temperature_peak",
461 "command": "0xDD",
462 "format": "linear_11"
463 }
464 },
465 {
466 "comments": [
467 "Read output voltage from READ_VOUT.",
468 "Note: regulator does not support VOUT_MODE, so the",
469 "exponent must be specified."
470 ],
471 "pmbus_read_sensor": {
472 "type": "vout",
473 "command": "0x8B",
474 "format": "linear_16",
475 "exponent": -8
476 }
477 },
478 {
479 "comments": [
480 "Read highest output voltage from MFR_VOUT_PEAK.",
481 "Note: regulator does not support VOUT_MODE, so the",
482 "exponent must be specified."
483 ],
484 "pmbus_read_sensor": {
485 "type": "vout_peak",
486 "command": "0xDB",
487 "format": "linear_16",
488 "exponent": -8
489 }
490 }
491 ]
492 },
493
494 {
495 "comments": [
496 "Rule to read sensors on IR35221 regulators using the",
497 "PMBus interface"
498 ],
499 "id": "read_sensors_ir35221_rule",
500 "actions": [
501 {
502 "comments": ["Read output current from READ_IOUT"],
503 "pmbus_read_sensor": {
504 "type": "iout",
505 "command": "0x8C",
506 "format": "linear_11"
507 }
508 },
509 {
510 "comments": [
511 "Read highest output current from MFR_IOUT_PEAK"
512 ],
513 "pmbus_read_sensor": {
514 "type": "iout_peak",
515 "command": "0xC7",
516 "format": "linear_11"
517 }
518 },
519 {
520 "comments": [
521 "Read lowest output current from MFR_IOUT_VALLEY"
522 ],
523 "pmbus_read_sensor": {
524 "type": "iout_valley",
525 "command": "0xCB",
526 "format": "linear_11"
527 }
528 },
529 {
530 "comments": ["Read output power from READ_POUT"],
531 "pmbus_read_sensor": {
532 "type": "pout",
533 "command": "0x96",
534 "format": "linear_11"
535 }
536 },
537 {
538 "comments": ["Read temperature from READ_TEMPERATURE_1"],
539 "pmbus_read_sensor": {
540 "type": "temperature",
541 "command": "0x8D",
542 "format": "linear_11"
543 }
544 },
545 {
546 "comments": ["Read highest temperature from MFR_TEMP_PEAK"],
547 "pmbus_read_sensor": {
548 "type": "temperature_peak",
549 "command": "0xC8",
550 "format": "linear_11"
551 }
552 },
553 {
554 "comments": ["Read output voltage from READ_VOUT"],
555 "pmbus_read_sensor": {
556 "type": "vout",
557 "command": "0x8B",
558 "format": "linear_16"
559 }
560 },
561 {
562 "comments": [
563 "Read highest output voltage from MFR_VOUT_PEAK"
564 ],
565 "pmbus_read_sensor": {
566 "type": "vout_peak",
567 "command": "0xC6",
568 "format": "linear_16"
569 }
570 },
571 {
572 "comments": [
573 "Read lowest output voltage from MFR_VOUT_VALLEY"
574 ],
575 "pmbus_read_sensor": {
576 "type": "vout_valley",
577 "command": "0xCA",
578 "format": "linear_16"
579 }
580 }
581 ]
582 },
583
584 {
585 "comments": [
586 "Rule to read sensors on PAGE 0 of IR35221 regulators",
587 "using the PMBus interface"
588 ],
589 "id": "read_sensors_ir35221_page0_rule",
590 "actions": [
591 { "run_rule": "set_page0_rule" },
592 { "run_rule": "read_sensors_ir35221_rule" }
593 ]
594 },
595
596 {
597 "comments": [
598 "Rule to read sensors on PAGE 1 of IR35221 regulators",
599 "using the PMBus interface"
600 ],
601 "id": "read_sensors_ir35221_page1_rule",
602 "actions": [
603 { "run_rule": "set_page1_rule" },
604 { "run_rule": "read_sensors_ir35221_rule" }
605 ]
606 },
607
608 {
609 "comments": [
610 "Rule to read sensors on PAGE 0 of XDPE132G5C regulators",
611 "using the PMBus interface"
612 ],
613 "id": "read_sensors_xdpe132g5c_page0_rule",
614 "actions": [
615 {
616 "comments": ["Can use same rule as for IR35221 regulators"],
617 "run_rule": "read_sensors_ir35221_page0_rule"
618 }
619 ]
620 },
621
622 {
623 "comments": [
624 "Rule to determine if the current system is a 2S4U/2S2U.",
625 "2S systems have more regulators on the Nisqually system",
626 "planar than 1S systems. Must return true if system is a",
627 "2S4U/2S2U and false if system is a 1S4U."
628 ],
629 "id": "is_2s_system_rule",
630 "actions": [
631 {
632 "comments": [
633 "Check whether the CCIN VPD keyword on the Nisqually",
634 "system planar has the value for 2S4U or 2S2U"
635 ],
636 "or": [
637 {
638 "compare_vpd": {
639 "fru": "system/chassis/motherboard",
640 "keyword": "CCIN",
641 "value": "2E2F"
642 }
643 },
644 {
645 "compare_vpd": {
646 "fru": "system/chassis/motherboard",
647 "keyword": "CCIN",
648 "value": "2E2D"
649 }
650 }
651 ]
652 }
653 ]
654 },
655
656 {
657 "comments": [
658 "Rule to determine if pass 2 or higher Nisqually",
659 "backplane is present. Must return true if present and",
660 "false otherwise."
661 ],
662 "id": "is_pass2_nisqually_rule",
663 "actions": [
664 {
665 "comments": [
666 "Check that the PartNumber VPD keyword on the",
667 "Nisqually system planar is not the value for",
668 "the pass 1 2U or 4U."
669 ],
670 "not": {
671 "or": [
672 {
673 "compare_vpd": {
674 "fru": "system/chassis/motherboard",
675 "keyword": "PartNumber",
676 "value": "02WG656"
677 }
678 },
679 {
680 "compare_vpd": {
681 "fru": "system/chassis/motherboard",
682 "keyword": "PartNumber",
683 "value": "02WG678"
684 }
685 }
686 ]
687 }
688 }
689 ]
690 },
691
692 {
693 "comments": [
694 "Rule to determine if the VRM FRU for DCM-1 is present.",
695 "Must return true if VRM is present and false if VRM is",
696 "missing."
697 ],
698 "id": "is_dcm1_vrm_present_rule",
699 "actions": [
700 {
701 "comments": [
702 "Check whether the VRM FRU is present OR the DCM-1",
Shawn McCarneyd97aa512022-03-24 19:02:32 -0500[diff] [blame]703 "FRU is present. This provides a double check in",
704 "case the VRM presence line is not working. If DCM-1",
Patrick Williams0dbce562022-12-12 10:43:31 -0600[diff] [blame]705 "is present, the associated VRM should be too."
706 ],
707 "or": [
708 {
709 "compare_presence": {
710 "fru": "system/chassis/motherboard/vdd_vrm1",
711 "value": true
Shawn McCarneyd97aa512022-03-24 19:02:32 -0500[diff] [blame]712 }
Shawn McCarneyd97aa512022-03-24 19:02:32 -0500[diff] [blame]713 },
Patrick Williams0dbce562022-12-12 10:43:31 -0600[diff] [blame]714 {
715 "compare_presence": {
716 "fru": "system/chassis/motherboard/dcm1/cpu0",
717 "value": true
Shawn McCarneyd97aa512022-03-24 19:02:32 -0500[diff] [blame]718 }
Patrick Williams0dbce562022-12-12 10:43:31 -0600[diff] [blame]719 }
720 ]
Shawn McCarneyd97aa512022-03-24 19:02:32 -0500[diff] [blame]721 }
Shawn McCarneyd97aa512022-03-24 19:02:32 -0500[diff] [blame]722 ]
Shawn McCarneyd97aa512022-03-24 19:02:32 -0500[diff] [blame]723 },
724
Patrick Williams0dbce562022-12-12 10:43:31 -0600[diff] [blame]725 {
726 "comments": [
727 "Rule to determine if a Flett card is present in slot C8.",
728 "This requires a Nisqually pass2+ due to I2C bus number",
729 "differences between pass 1 and pass 2.",
730 "Pass 1 and pass 2 Fletts are both supported.",
731 "Must return true if present and false otherwise."
732 ],
733 "id": "is_flett_c8_present_rule",
734 "actions": [
735 {
736 "if": {
737 "condition": {
738 "comments": ["Check if the Nisqually is pass 2"],
739 "run_rule": "is_pass2_nisqually_rule"
740 },
741 "then": [
742 {
743 "comments": [
744 "Check if a card is present in slot C8"
745 ],
746 "if": {
747 "condition": {
748 "compare_presence": {
749 "fru": "system/chassis/motherboard/pcieslot8/pcie_card8",
750 "value": true
751 }
752 },
753 "then": [
754 {
755 "comments": [
756 "Check if card has Flett CCIN keyword"
757 ],
758 "compare_vpd": {
759 "fru": "system/chassis/motherboard/pcieslot8/pcie_card8",
760 "keyword": "CCIN",
761 "value": "6B87"
762 }
763 }
764 ]
765 }
766 }
767 ]
768 }
769 }
770 ]
771 },
Shawn McCarneyd97aa512022-03-24 19:02:32 -0500[diff] [blame]772
773 {
Patrick Williams0dbce562022-12-12 10:43:31 -0600[diff] [blame]774 "comments": [
775 "Rule to determine if a Flett card is present in slot C9.",
776 "This requires a Nisqually pass2+ due to I2C bus number",
777 "differences between pass 1 and pass 2.",
778 "This also requires the Flett to be pass 2 because the",
779 "pass 1 regulator has a different I2C address.",
780 "Must return true if present and false otherwise."
781 ],
782 "id": "is_flett_c9_present_rule",
783 "actions": [
784 {
785 "if": {
786 "condition": {
787 "comments": ["Check if the Nisqually is pass 2"],
788 "run_rule": "is_pass2_nisqually_rule"
789 },
790 "then": [
791 {
792 "comments": [
793 "Check if a card is present in slot C9"
794 ],
795 "if": {
796 "condition": {
797 "compare_presence": {
798 "fru": "system/chassis/motherboard/pcieslot9/pcie_card9",
799 "value": true
800 }
801 },
802 "then": [
803 {
804 "comments": [
805 "Check if card has Flett CCIN keyword"
806 ],
807 "if": {
808 "condition": {
809 "compare_vpd": {
810 "fru": "system/chassis/motherboard/pcieslot9/pcie_card9",
811 "keyword": "CCIN",
812 "value": "6B87"
813 }
814 },
815 "then": [
816 {
817 "comments": [
818 "Check that card does not have a pass 1",
819 "part number"
820 ],
821 "not": {
822 "or": [
823 {
824 "compare_vpd": {
825 "fru": "system/chassis/motherboard/pcieslot9/pcie_card9",
826 "keyword": "PartNumber",
827 "value": "03FL194"
828 }
829 },
830 {
831 "compare_vpd": {
832 "fru": "system/chassis/motherboard/pcieslot9/pcie_card9",
833 "keyword": "PartNumber",
834 "value": "03FL204"
835 }
836 }
837 ]
838 }
839 }
840 ]
841 }
842 }
843 ]
844 }
845 }
846 ]
847 }
848 }
849 ]
850 },
851
852 {
853 "comments": [
854 "Rule to determine if a Flett card is present in slot C10.",
855 "This requires a Nisqually pass2+ due to I2C bus number",
856 "differences between pass 1 and pass 2.",
857 "This also requires the Flett to be pass 2 because the",
858 "pass 1 regulator has a different I2C address.",
859 "Must return true if present and false otherwise."
860 ],
861 "id": "is_flett_c10_present_rule",
862 "actions": [
863 {
864 "if": {
865 "condition": {
866 "comments": ["Check if the Nisqually is pass 2"],
867 "run_rule": "is_pass2_nisqually_rule"
868 },
869 "then": [
870 {
871 "comments": [
872 "Check if a card is present in slot C10"
873 ],
874 "if": {
875 "condition": {
876 "compare_presence": {
877 "fru": "system/chassis/motherboard/pcieslot10/pcie_card10",
878 "value": true
879 }
880 },
881 "then": [
882 {
883 "comments": [
884 "Check if card has Flett CCIN keyword"
885 ],
886 "if": {
887 "condition": {
888 "compare_vpd": {
889 "fru": "system/chassis/motherboard/pcieslot10/pcie_card10",
890 "keyword": "CCIN",
891 "value": "6B87"
892 }
893 },
894 "then": [
895 {
896 "comments": [
897 "Check that card does not have a pass 1",
898 "part number"
899 ],
900 "not": {
901 "or": [
902 {
903 "compare_vpd": {
904 "fru": "system/chassis/motherboard/pcieslot10/pcie_card10",
905 "keyword": "PartNumber",
906 "value": "03FL194"
907 }
908 },
909 {
910 "compare_vpd": {
911 "fru": "system/chassis/motherboard/pcieslot10/pcie_card10",
912 "keyword": "PartNumber",
913 "value": "03FL204"
914 }
915 }
916 ]
917 }
918 }
919 ]
920 }
921 }
922 ]
923 }
924 }
925 ]
926 }
927 }
928 ]
929 },
930
931 {
932 "comments": [
933 "Rule to determine if a Flett card is present in slot C11.",
934 "This requires a Nisqually pass2+ due to I2C bus number",
935 "differences between pass 1 and pass 2.",
936 "Pass 1 and pass 2 Fletts are both supported.",
937 "Must return true if present and false otherwise."
938 ],
939 "id": "is_flett_c11_present_rule",
940 "actions": [
941 {
942 "if": {
943 "condition": {
944 "comments": ["Check if the Nisqually is pass 2"],
945 "run_rule": "is_pass2_nisqually_rule"
946 },
947 "then": [
948 {
949 "comments": [
950 "Check if a card is present in slot C11"
951 ],
952 "if": {
953 "condition": {
954 "compare_presence": {
955 "fru": "system/chassis/motherboard/pcieslot11/pcie_card11",
956 "value": true
957 }
958 },
959 "then": [
960 {
961 "comments": [
962 "Check if card has Flett CCIN keyword"
963 ],
964 "compare_vpd": {
965 "fru": "system/chassis/motherboard/pcieslot11/pcie_card11",
966 "keyword": "CCIN",
967 "value": "6B87"
968 }
969 }
970 ]
971 }
972 }
973 ]
974 }
975 }
976 ]
977 }
978 ],
979
980 "chassis": [
981 {
982 "comments": ["Chassis (drawer) 1"],
983 "number": 1,
984 "inventory_path": "system/chassis",
985 "devices": [
986 {
987 "comments": [
988 "AVDD / IR38064: Primary PMBus Interface",
989 "In schematic: bus 4 (1-based), address 0xE2 (8-bit)"
990 ],
991 "id": "avdd_regulator",
992 "is_regulator": true,
993 "fru": "system/chassis/motherboard",
994 "i2c_interface": { "bus": 3, "address": "0x71" },
995 "presence_detection": {
996 "rule_id": "is_pass2_nisqually_rule"
997 },
998 "rails": [
999 {
1000 "id": "avdd_rail",
1001 "sensor_monitoring": {
1002 "rule_id": "read_sensors_ir38064_rule"
1003 }
1004 }
1005 ]
1006 },
1007
1008 {
1009 "comments": [
1010 "3.3VA / TPS549D22",
Shawn McCarneyd97aa512022-03-24 19:02:32 -0500[diff] [blame]1011 "In schematic: bus 9 (1-based), address 0x36 (8-bit)",
1012 "Does not have power at standby; cannot be configured",
Patrick Williams0dbce562022-12-12 10:43:31 -0600[diff] [blame]1013 "Does not support the PMBus PAGE command"
1014 ],
1015 "id": "3_3va_regulator",
1016 "is_regulator": true,
1017 "fru": "system/chassis/motherboard",
1018 "i2c_interface": { "bus": 8, "address": "0x1B" },
1019 "rails": [
1020 {
1021 "id": "3_3va_rail"
1022 }
1023 ]
1024 },
Shawn McCarneyd97aa512022-03-24 19:02:32 -0500[diff] [blame]1025
Patrick Williams0dbce562022-12-12 10:43:31 -0600[diff] [blame]1026 {
1027 "comments": [
1028 "3.3VB / TPS549D22",
Shawn McCarneyd97aa512022-03-24 19:02:32 -0500[diff] [blame]1029 "In schematic: bus 4 (1-based), address 0x38 (8-bit)",
1030 "Does not have power at standby; cannot be configured",
Patrick Williams0dbce562022-12-12 10:43:31 -0600[diff] [blame]1031 "Does not support the PMBus PAGE command"
1032 ],
1033 "id": "3_3vb_regulator",
1034 "is_regulator": true,
1035 "fru": "system/chassis/motherboard",
1036 "i2c_interface": { "bus": 3, "address": "0x1C" },
1037 "rails": [
1038 {
1039 "id": "3_3vb_rail"
1040 }
1041 ]
1042 },
Shawn McCarneyd97aa512022-03-24 19:02:32 -0500[diff] [blame]1043
Patrick Williams0dbce562022-12-12 10:43:31 -0600[diff] [blame]1044 {
1045 "comments": [
1046 "VDDp0 DCM 0 / XDPE132G5C: Primary PMBus Interface",
1047 "In schematic: bus 10 (1-based), address 0xE2 (8-bit)"
1048 ],
1049 "id": "vdd_p0_dcm0_regulator",
1050 "is_regulator": true,
1051 "fru": "system/chassis/motherboard/vdd_vrm0",
1052 "i2c_interface": { "bus": 9, "address": "0x71" },
1053 "rails": [
1054 {
1055 "id": "vdd_p0_dcm0_rail",
1056 "configuration": {
1057 "volts": 0.9,
1058 "rule_id": "configure_vdd_rule"
1059 },
1060 "sensor_monitoring": {
1061 "rule_id": "read_sensors_xdpe132g5c_page0_rule"
1062 }
1063 }
1064 ]
1065 },
Shawn McCarneyd97aa512022-03-24 19:02:32 -0500[diff] [blame]1066
Patrick Williams0dbce562022-12-12 10:43:31 -0600[diff] [blame]1067 {
1068 "comments": [
1069 "VDDp1 DCM 0 / XDPE132G5C: Primary PMBus Interface",
1070 "In schematic: bus 10 (1-based), address 0xE0 (8-bit)"
1071 ],
1072 "id": "vdd_p1_dcm0_regulator",
1073 "is_regulator": true,
1074 "fru": "system/chassis/motherboard/vdd_vrm0",
1075 "i2c_interface": { "bus": 9, "address": "0x70" },
1076 "rails": [
1077 {
1078 "id": "vdd_p1_dcm0_rail",
1079 "configuration": {
1080 "volts": 0.9,
1081 "rule_id": "configure_vdd_rule"
1082 },
1083 "sensor_monitoring": {
1084 "rule_id": "read_sensors_xdpe132g5c_page0_rule"
1085 }
1086 }
1087 ]
1088 },
Shawn McCarneyd97aa512022-03-24 19:02:32 -0500[diff] [blame]1089
Patrick Williams0dbce562022-12-12 10:43:31 -0600[diff] [blame]1090 {
1091 "comments": [
1092 "VDDp0 DCM 1 / XDPE132G5C: Primary PMBus Interface",
1093 "In schematic: bus 11 (1-based), address 0xE2 (8-bit)"
1094 ],
1095 "id": "vdd_p0_dcm1_regulator",
1096 "is_regulator": true,
1097 "fru": "system/chassis/motherboard/vdd_vrm1",
1098 "i2c_interface": { "bus": 10, "address": "0x71" },
1099 "presence_detection": {
1100 "rule_id": "is_dcm1_vrm_present_rule"
1101 },
1102 "rails": [
1103 {
1104 "id": "vdd_p0_dcm1_rail",
1105 "configuration": {
1106 "volts": 0.9,
1107 "rule_id": "configure_vdd_rule"
1108 },
1109 "sensor_monitoring": {
1110 "rule_id": "read_sensors_xdpe132g5c_page0_rule"
1111 }
1112 }
1113 ]
1114 },
Shawn McCarneyd97aa512022-03-24 19:02:32 -0500[diff] [blame]1115
Patrick Williams0dbce562022-12-12 10:43:31 -0600[diff] [blame]1116 {
1117 "comments": [
1118 "VDDp1 DCM 1 / XDPE132G5C: Primary PMBus Interface",
1119 "In schematic: bus 11 (1-based), address 0xE0 (8-bit)"
1120 ],
1121 "id": "vdd_p1_dcm1_regulator",
1122 "is_regulator": true,
1123 "fru": "system/chassis/motherboard/vdd_vrm1",
1124 "i2c_interface": { "bus": 10, "address": "0x70" },
1125 "presence_detection": {
1126 "rule_id": "is_dcm1_vrm_present_rule"
1127 },
1128 "rails": [
1129 {
1130 "id": "vdd_p1_dcm1_rail",
1131 "configuration": {
1132 "volts": 0.9,
1133 "rule_id": "configure_vdd_rule"
1134 },
1135 "sensor_monitoring": {
1136 "rule_id": "read_sensors_xdpe132g5c_page0_rule"
1137 }
1138 }
1139 ]
1140 },
Shawn McCarneyd97aa512022-03-24 19:02:32 -0500[diff] [blame]1141
Patrick Williams0dbce562022-12-12 10:43:31 -0600[diff] [blame]1142 {
1143 "comments": [
1144 "VDN & VCSp0 DCM 0 / IR35221: Primary PMBus Interface",
1145 "In schematic: bus 10 (1-based), address 0xE4 (8-bit)"
1146 ],
1147 "id": "vdn_vcs_p0_dcm0_regulator",
1148 "is_regulator": true,
1149 "fru": "system/chassis/motherboard",
1150 "i2c_interface": { "bus": 9, "address": "0x72" },
1151 "rails": [
1152 {
1153 "comments": ["PMBus PAGE 0 rail"],
1154 "id": "vdn_dcm0_rail",
1155 "configuration": {
1156 "volts": 0.9,
1157 "rule_id": "configure_vdn_rule"
1158 },
1159 "sensor_monitoring": {
1160 "rule_id": "read_sensors_ir35221_page0_rule"
1161 }
1162 },
1163 {
1164 "comments": ["PMBus PAGE 1 rail"],
1165 "id": "vcs_p0_dcm0_rail",
1166 "configuration": {
1167 "volts": 1.0,
1168 "rule_id": "configure_vcs_rule"
1169 },
1170 "sensor_monitoring": {
1171 "rule_id": "read_sensors_ir35221_page1_rule"
1172 }
1173 }
1174 ]
1175 },
Shawn McCarneyd97aa512022-03-24 19:02:32 -0500[diff] [blame]1176
Patrick Williams0dbce562022-12-12 10:43:31 -0600[diff] [blame]1177 {
1178 "comments": [
1179 "VIO & VCSp1 DCM 0 / IR35221: Primary PMBus Interface",
1180 "In schematic: bus 10 (1-based), address 0xE6 (8-bit)"
1181 ],
1182 "id": "vio_vcs_p1_dcm0_regulator",
1183 "is_regulator": true,
1184 "fru": "system/chassis/motherboard",
1185 "i2c_interface": { "bus": 9, "address": "0x73" },
1186 "rails": [
1187 {
1188 "comments": ["PMBus PAGE 0 rail"],
1189 "id": "vio_dcm0_rail",
1190 "configuration": {
1191 "volts": 1.02,
1192 "rule_id": "configure_vio_rule"
1193 },
1194 "sensor_monitoring": {
1195 "rule_id": "read_sensors_ir35221_page0_rule"
1196 }
1197 },
1198 {
1199 "comments": ["PMBus PAGE 1 rail"],
1200 "id": "vcs_p1_dcm0_rail",
1201 "configuration": {
1202 "volts": 1.0,
1203 "rule_id": "configure_vcs_rule"
1204 },
1205 "sensor_monitoring": {
1206 "rule_id": "read_sensors_ir35221_page1_rule"
1207 }
1208 }
1209 ]
1210 },
Shawn McCarneyd97aa512022-03-24 19:02:32 -0500[diff] [blame]1211
Patrick Williams0dbce562022-12-12 10:43:31 -0600[diff] [blame]1212 {
1213 "comments": [
1214 "VDN & VCSp0 DCM 1 / IR35221: Primary PMBus Interface",
1215 "In schematic: bus 11 (1-based), address 0xE4 (8-bit)"
1216 ],
1217 "id": "vdn_vcs_p0_dcm1_regulator",
1218 "is_regulator": true,
1219 "fru": "system/chassis/motherboard",
1220 "i2c_interface": { "bus": 10, "address": "0x72" },
1221 "presence_detection": { "rule_id": "is_2s_system_rule" },
1222 "rails": [
1223 {
1224 "comments": ["PMBus PAGE 0 rail"],
1225 "id": "vdn_dcm1_rail",
1226 "configuration": {
1227 "volts": 0.9,
1228 "rule_id": "configure_vdn_rule"
1229 },
1230 "sensor_monitoring": {
1231 "rule_id": "read_sensors_ir35221_page0_rule"
1232 }
1233 },
1234 {
1235 "comments": ["PMBus PAGE 1 rail"],
1236 "id": "vcs_p0_dcm1_rail",
1237 "configuration": {
1238 "volts": 1.0,
1239 "rule_id": "configure_vcs_rule"
1240 },
1241 "sensor_monitoring": {
1242 "rule_id": "read_sensors_ir35221_page1_rule"
1243 }
1244 }
1245 ]
1246 },
Shawn McCarneyd97aa512022-03-24 19:02:32 -0500[diff] [blame]1247
Patrick Williams0dbce562022-12-12 10:43:31 -0600[diff] [blame]1248 {
1249 "comments": [
1250 "VIO & VCSp1 DCM 1 / IR35221: Primary PMBus Interface",
1251 "In schematic: bus 11 (1-based), address 0xE6 (8-bit)"
1252 ],
1253 "id": "vio_vcs_p1_dcm1_regulator",
1254 "is_regulator": true,
1255 "fru": "system/chassis/motherboard",
1256 "i2c_interface": { "bus": 10, "address": "0x73" },
1257 "presence_detection": { "rule_id": "is_2s_system_rule" },
1258 "rails": [
1259 {
1260 "comments": ["PMBus PAGE 0 rail"],
1261 "id": "vio_dcm1_rail",
1262 "configuration": {
1263 "volts": 1.02,
1264 "rule_id": "configure_vio_rule"
1265 },
1266 "sensor_monitoring": {
1267 "rule_id": "read_sensors_ir35221_page0_rule"
1268 }
1269 },
1270 {
1271 "comments": ["PMBus PAGE 1 rail"],
1272 "id": "vcs_p1_dcm1_rail",
1273 "configuration": {
1274 "volts": 1.0,
1275 "rule_id": "configure_vcs_rule"
1276 },
1277 "sensor_monitoring": {
1278 "rule_id": "read_sensors_ir35221_page1_rule"
1279 }
1280 }
1281 ]
1282 },
Shawn McCarneyd97aa512022-03-24 19:02:32 -0500[diff] [blame]1283
Patrick Williams0dbce562022-12-12 10:43:31 -0600[diff] [blame]1284 {
1285 "comments": [
1286 "VPCIe DCM 0 / IR35221: Primary PMBus Interface",
1287 "In schematic: bus 10 (1-based), address 0xE8 (8-bit)"
1288 ],
1289 "id": "vpcie_dcm0_regulator",
1290 "is_regulator": true,
1291 "fru": "system/chassis/motherboard",
1292 "i2c_interface": { "bus": 9, "address": "0x74" },
1293 "rails": [
1294 {
1295 "id": "vpcie_dcm0_rail",
1296 "configuration": {
1297 "volts": 0.86,
1298 "rule_id": "configure_vpcie_rule"
1299 },
1300 "sensor_monitoring": {
1301 "rule_id": "read_sensors_ir35221_page0_rule"
1302 }
1303 }
1304 ]
1305 },
Shawn McCarneyd97aa512022-03-24 19:02:32 -0500[diff] [blame]1306
Patrick Williams0dbce562022-12-12 10:43:31 -0600[diff] [blame]1307 {
1308 "comments": [
1309 "VPCIe DCM 1 / IR35221: Primary PMBus Interface",
1310 "In schematic: bus 11 (1-based), address 0xE8 (8-bit)"
1311 ],
1312 "id": "vpcie_dcm1_regulator",
1313 "is_regulator": true,
1314 "fru": "system/chassis/motherboard",
1315 "i2c_interface": { "bus": 10, "address": "0x74" },
1316 "presence_detection": { "rule_id": "is_2s_system_rule" },
1317 "rails": [
1318 {
1319 "id": "vpcie_dcm1_rail",
1320 "configuration": {
1321 "volts": 0.86,
1322 "rule_id": "configure_vpcie_rule"
1323 },
1324 "sensor_monitoring": {
1325 "rule_id": "read_sensors_ir35221_page0_rule"
1326 }
1327 }
1328 ]
1329 },
Shawn McCarneyd97aa512022-03-24 19:02:32 -0500[diff] [blame]1330
Patrick Williams0dbce562022-12-12 10:43:31 -0600[diff] [blame]1331 {
1332 "comments": [
1333 "Flett Slot C8 / IR35221: Primary PMBus Interface",
Shawn McCarneyd97aa512022-03-24 19:02:32 -0500[diff] [blame]1334 "In schematic: bus 7 (1-based) mux channel 3,",
1335 "address 0xEC (8-bit).",
Patrick Williams0dbce562022-12-12 10:43:31 -0600[diff] [blame]1336 "BMC I2C bus alias 28"
1337 ],
1338 "id": "flett_slot_c8_regulator",
1339 "is_regulator": true,
1340 "fru": "system/chassis/motherboard/pcieslot8/pcie_card8",
1341 "i2c_interface": { "bus": 28, "address": "0x76" },
1342 "presence_detection": {
1343 "rule_id": "is_flett_c8_present_rule"
1344 },
1345 "rails": [
1346 {
1347 "id": "flett_slot_c8_rail",
1348 "sensor_monitoring": {
1349 "rule_id": "read_sensors_ir35221_page0_rule"
1350 }
1351 }
1352 ]
1353 },
Shawn McCarneyd97aa512022-03-24 19:02:32 -0500[diff] [blame]1354
Patrick Williams0dbce562022-12-12 10:43:31 -0600[diff] [blame]1355 {
1356 "comments": [
1357 "Flett Slot C9 / IR35221: Primary PMBus Interface",
Shawn McCarneyd97aa512022-03-24 19:02:32 -0500[diff] [blame]1358 "In schematic: bus 7 (1-based) mux channel 2,",
1359 "address 0xEC (8-bit).",
Patrick Williams0dbce562022-12-12 10:43:31 -0600[diff] [blame]1360 "BMC I2C bus alias 27"
1361 ],
1362 "id": "flett_slot_c9_regulator",
1363 "is_regulator": true,
1364 "fru": "system/chassis/motherboard/pcieslot9/pcie_card9",
1365 "i2c_interface": { "bus": 27, "address": "0x76" },
1366 "presence_detection": {
1367 "rule_id": "is_flett_c9_present_rule"
1368 },
1369 "rails": [
1370 {
1371 "id": "flett_slot_c9_rail",
1372 "sensor_monitoring": {
1373 "rule_id": "read_sensors_ir35221_page0_rule"
1374 }
1375 }
1376 ]
1377 },
Shawn McCarneyd97aa512022-03-24 19:02:32 -0500[diff] [blame]1378
Patrick Williams0dbce562022-12-12 10:43:31 -0600[diff] [blame]1379 {
1380 "comments": [
1381 "Flett Slot C11 / IR35221: Primary PMBus Interface",
Shawn McCarneyd97aa512022-03-24 19:02:32 -0500[diff] [blame]1382 "In schematic: bus 12 (1-based) mux channel 1,",
1383 "address 0xEC (8-bit).",
Patrick Williams0dbce562022-12-12 10:43:31 -0600[diff] [blame]1384 "BMC I2C bus alias 30"
1385 ],
1386 "id": "flett_slot_c11_regulator",
1387 "is_regulator": true,
1388 "fru": "system/chassis/motherboard/pcieslot11/pcie_card11",
1389 "i2c_interface": { "bus": 30, "address": "0x76" },
1390 "presence_detection": {
1391 "rule_id": "is_flett_c11_present_rule"
1392 },
1393 "rails": [
1394 {
1395 "id": "flett_slot_c11_rail",
1396 "sensor_monitoring": {
1397 "rule_id": "read_sensors_ir35221_page0_rule"
1398 }
1399 }
1400 ]
1401 },
Shawn McCarneyd97aa512022-03-24 19:02:32 -0500[diff] [blame]1402
Patrick Williams0dbce562022-12-12 10:43:31 -0600[diff] [blame]1403 {
1404 "comments": [
1405 "Flett Slot C10 / IR35221: Primary PMBus Interface",
Shawn McCarneyd97aa512022-03-24 19:02:32 -0500[diff] [blame]1406 "In schematic: bus 12 (1-based) mux channel 0,",
1407 "address 0xEC (8-bit).",
Patrick Williams0dbce562022-12-12 10:43:31 -0600[diff] [blame]1408 "BMC I2C bus alias 29"
1409 ],
1410 "id": "flett_slot_c10_regulator",
1411 "is_regulator": true,
1412 "fru": "system/chassis/motherboard/pcieslot10/pcie_card10",
1413 "i2c_interface": { "bus": 29, "address": "0x76" },
1414 "presence_detection": {
1415 "rule_id": "is_flett_c10_present_rule"
1416 },
1417 "rails": [
1418 {
1419 "id": "flett_slot_c10_rail",
1420 "sensor_monitoring": {
1421 "rule_id": "read_sensors_ir35221_page0_rule"
1422 }
1423 }
1424 ]
1425 }
1426 ]
Shawn McCarneyd97aa512022-03-24 19:02:32 -0500[diff] [blame]1427 }
Patrick Williams0dbce562022-12-12 10:43:31 -0600[diff] [blame]1428 ]
Shawn McCarney46b5e692020-04-30 16:34:39 -0500[diff] [blame]1429}