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gerrit.openbmc.org / premsjha / op-build / 591d53cbdb64be29c4daae3555d7b52c3f395e21 / . / openpower / package / hostboot / hostboot-0001-Disable-centaur-memory-throttle.patch
blob: 06eb3f1d61eabfe061ea660ac65c492c8d25b1c0 [file] [log] [blame]
Brian Silver131189b2014-11-10 08:11:22 -0600[diff] [blame]1From 79836dad6267a420ccdd5d3a050ea012227cc9e3 Mon Sep 17 00:00:00 2001
2From: Dean Sanner <dsanner@us.ibm.com>
3Date: Thu, 30 Oct 2014 10:39:12 -0500
4Subject: [PATCH] Disable centaur memory throttle
5
6Change-Id: I86098af366a60b8132f802d8304f1ef883cff542
7---
8 .../mss_thermal_init/mss_thermal_init.C | 3 +-
9 src/usr/hwpf/hwp/initfiles/mba_def.initfile | 49 ----------------------
10 2 files changed, 2 insertions(+), 50 deletions(-)
11
12diff --git a/src/usr/hwpf/hwp/dram_initialization/mss_thermal_init/mss_thermal_init.C b/src/usr/hwpf/hwp/dram_initialization/mss_thermal_init/mss_thermal_init.C
13index c295d0f..c607f9b 100644
14--- a/src/usr/hwpf/hwp/dram_initialization/mss_thermal_init/mss_thermal_init.C
15+++ b/src/usr/hwpf/hwp/dram_initialization/mss_thermal_init/mss_thermal_init.C
16@@ -586,7 +586,7 @@ fapi::ReturnCode mss_thermal_init(const fapi::Target & i_target)
17
18 // Write the IPL Safe Mode Throttles
19 // For centaur DD2 and above since OCC only writes runtime throttles for this
20-
21+#if 0
22 uint8_t l_enable_safemode_throttle = 0;
23 l_rc = FAPI_ATTR_GET(ATTR_CENTAUR_EC_ENABLE_SAFEMODE_THROTTLE, &i_target, l_enable_safemode_throttle);
24 if (l_rc) return l_rc;
25@@ -618,6 +618,7 @@ fapi::ReturnCode mss_thermal_init(const fapi::Target & i_target)
26 if (l_rc) return l_rc;
27 }
28 }
29+#endif
30
31 FAPI_INF("*** %s COMPLETE ***", procedure_name);
32 return l_rc;
33diff --git a/src/usr/hwpf/hwp/initfiles/mba_def.initfile b/src/usr/hwpf/hwp/initfiles/mba_def.initfile
34index 4a66dca..2dad4f4 100644
35--- a/src/usr/hwpf/hwp/initfiles/mba_def.initfile
36+++ b/src/usr/hwpf/hwp/initfiles/mba_def.initfile
37@@ -1516,55 +1516,6 @@ scom 0x0301040E {
38 #cfg_nm_ras_weight, bits 45:47 = ATTR_MSS_THROTTLE_CONTROL_RAS_WEIGHT
39 #cfg_nm_cas_weight, bits 48:50 = ATTR_MSS_THROTTLE_CONTROL_CAS_WEIGHT
40
41-
42-
43-scom 0x03010416 {
44- bits , scom_data , ATTR_FUNCTIONAL, expr;
45- 0:14 , ATTR_MSS_MEM_THROTTLE_NUMERATOR_PER_MBA , 1 , any; # cfg_nm_n_per_mba MSS_MEM_THROTTLE_NUMERATOR_PER_MBA
46- 15:30 , ATTR_MSS_MEM_THROTTLE_NUMERATOR_PER_CHIP , 1 , any; # cfg_nm_n_per_chip MSS_MEM_THROTTLE_NUMERATOR_PER_CHIP
47- 31:44 , ATTR_MSS_MEM_THROTTLE_DENOMINATOR , 1 , any; # cfg_nm_m MSS_MEM_THROTTLE_DENOMINATOR
48- 45:47 , ATTR_MSS_THROTTLE_CONTROL_RAS_WEIGHT , 1 , any; # cfg_nm_ras_weight
49- 48:50 , ATTR_MSS_THROTTLE_CONTROL_CAS_WEIGHT , 1 , any; # cfg_nm_cas_weight
50- 51 , 0b0 , 1 , (ATTR_EFF_DIMM_TYPE == 2 ) && (ATTR_EFF_CUSTOM_DIMM == 1); # cfg_nm_per_slot_enabled Set to 0 for CDIMM, Set to 1 for everything else
51- 51 , 0b1 , 1 , ((ATTR_EFF_DIMM_TYPE == 1) || ((ATTR_EFF_DIMM_TYPE == 2) && (ATTR_EFF_CUSTOM_DIMM == 0)) || (ATTR_EFF_DIMM_TYPE == 3)); # cfg_nm_per_slot_enabled Set to 0 for CDIMM, Set to 1 for everything else
52- 52 , 0b0 , 1 , (ATTR_EFF_DIMM_TYPE == 2) && (ATTR_EFF_CUSTOM_DIMM == 1); # cfg_nm_count_other_mba_dis Set to 0 for CDIMM, Set to 1 for everything else
53- 52 , 0b1 , 1 , ((ATTR_EFF_DIMM_TYPE == 1) || ((ATTR_EFF_DIMM_TYPE == 2) && (ATTR_EFF_CUSTOM_DIMM == 0)) || (ATTR_EFF_DIMM_TYPE == 3)); # cfg_nm_count_other_mba_dis Set to 0 for CDIMM, Set to 1 for everything else
54- 53 , 0b1 , 1 , (ATTR_CENTAUR_EC_ENABLE_NM_CHANGE_AFTER_SYNC == 1); # cfg_nm_change_after_sync
55-}
56-
57-
58-#Register Name N/M Throttling Control
59-#Mnemonic MBA_FARB4Q
60-#Attributes PAR:EVEN Bit Field Mnemonic Attribute or Setting to use
61-#Description N/M throttling control (Centaur only)
62-#MBA_FARB4Q(0:1) cfg_rhmr_en 01 Track only (only FIRs will go off, signaling when a block would have occurred)
63-#MBA_FARB4Q(2) cfg_rhmr_secondary_en 0 Secondary Structure disabled (this is for repair sequence)
64-#MBA_FARB4Q(3) cfg_rhmr_hash_swizzle_en 0 Disable swizzling hash (so we don't switch which rows correspond to which counters)
65-#MBA_FARB4Q(4:9) Reserved 000000 Don't Care
66-#MBA_FARB4Q(10:11) cfg_rhmr_decrement_weight 01 Decrement by 1 (minimum weight)
67-#MBA_FARB4Q(12:18) cfg_rhmr_primary_decr_intv 1111111 Slowest rate of decrements. Once ever 2^14 or 16K DRAM clocks*
68-#MBA_FARB4Q(12:18) cfg_rhmr_primary_decr_intv 0000011 decrement every 512 DRAM clocks for 100K accesses to hash group
69-#MBA_FARB4Q(19:25) cfg_rhmr_secondary_decr_intv 0000000 Don't care
70-#MBA_FARB4Q(26) cfg_rhmr_sim_en 0 Disable sim mode
71-# -- bits 27:41 (cfg_emer_n) = ATTR_MRW_SAFEMODE_MEM_THROTTLE_NUMERATOR_PER_CHIP
72-# -- bits 42:55 (cfg_emer_m) = ATTR_MRW_MEM_THROTTLE_DENOMINATOR
73-#*I think this corresponds to protecting a row from being hammered 64K times.
74-
75-scom 0x03010417 {
76- bits , scom_data , ATTR_FUNCTIONAL, expr;
77- 0:1 , 0b01 , 1 , (ATTR_CENTAUR_EC_ENABLE_ROW_HAMMER_FEATURE == 1);
78- 2 , 0b0 , 1 , (ATTR_CENTAUR_EC_ENABLE_ROW_HAMMER_FEATURE == 1);
79- 3 , 0b0 , 1 , (ATTR_CENTAUR_EC_ENABLE_ROW_HAMMER_FEATURE == 1);
80- 4:9 , 0b000000 , 1 , (ATTR_CENTAUR_EC_ENABLE_ROW_HAMMER_FEATURE == 1);
81- 10:11 , 0b01 , 1 , (ATTR_CENTAUR_EC_ENABLE_ROW_HAMMER_FEATURE == 1);
82- 12:18 , 0b0000011 , 1 , (ATTR_CENTAUR_EC_ENABLE_ROW_HAMMER_FEATURE == 1);
83- 19:25 , 0b0000000 , 1 , (ATTR_CENTAUR_EC_ENABLE_ROW_HAMMER_FEATURE == 1);
84- 26 , 0b0 , 1 , (ATTR_CENTAUR_EC_ENABLE_ROW_HAMMER_FEATURE == 1);
85- 27:41 , SYS.ATTR_MRW_SAFEMODE_MEM_THROTTLE_NUMERATOR_PER_CHIP, 1 , (ATTR_CENTAUR_EC_ENABLE_SAFE_MODE_THROTTLE == 1);
86- 42:55 , SYS.ATTR_MRW_MEM_THROTTLE_DENOMINATOR , 1 , (ATTR_CENTAUR_EC_ENABLE_SAFE_MODE_THROTTLE == 1);
87-}
88-
89-
90 # ATTR_EFF_DIMM_TYPE
91 # CDIMM = 0, RDIMM = 1, UDIMM = 2, LRDIMM = 3
92
93--
941.9.1
95