blob: 2e5afed8b18f072e638b8c7bf033145d0bf17b58 [file] [log] [blame]
Andrew Geisslera9ff2b32020-10-16 10:11:54 -05001From b066cb189302814fcd91b38f2f9da830a2c5b8fe Mon Sep 17 00:00:00 2001
Brad Bishop26bdd442019-08-16 17:08:17 -04002From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Tue, 17 Jan 2017 18:07:24 +0530
Andrew Geisslera9ff2b32020-10-16 10:11:54 -05004Subject: [PATCH 22/58] [PATCH] microblaze.md: Improve 'adddi3' and 'subdi3'
5 insn definitions
6
7Change adddi3 to handle DI immediates as the second operand, this
8requires modification to the output template however reduces the need to
9specify seperate templates for 16-bit positive/negative immediate
10operands. The use of 32-bit immediates for the addi and addic
11instructions is handled by the assembler, which will emit the imm
12instructions when required. This conveniently handles the optimizable
13cases where the immediate constant value does not need the higher half
14words of the operands upper/lower words.
Brad Bishop286d45c2018-10-02 15:21:57 -040015
16Change the constraints of the subdi3 instruction definition such that it
17does not match the second operand as an immediate value. This is because
18there is no definition to handle this case nor is it possible to
19implement purely with instructions as microblaze does not provide an
20instruction to perform a forward arithmetic subtraction (it only
21provides reverse 'rD = IMM - rA').
22
23Signed-off-by: Nathan Rossi <nathan@nathanrossi.com>
Brad Bishop286d45c2018-10-02 15:21:57 -040024---
25 gcc/config/microblaze/microblaze.md | 13 ++++++-------
26 1 file changed, 6 insertions(+), 7 deletions(-)
27
28diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
Andrew Geisslera9ff2b32020-10-16 10:11:54 -050029index 986d9c3aa25..efd2c34e0b7 100644
Brad Bishop286d45c2018-10-02 15:21:57 -040030--- a/gcc/config/microblaze/microblaze.md
31+++ b/gcc/config/microblaze/microblaze.md
Andrew Geissler84ad7c52020-06-27 00:00:16 -050032@@ -502,17 +502,16 @@
Brad Bishop286d45c2018-10-02 15:21:57 -040033 ;; Adding 2 DI operands in register or reg/imm
34
35 (define_insn "adddi3"
36- [(set (match_operand:DI 0 "register_operand" "=d,d,d")
37- (plus:DI (match_operand:DI 1 "register_operand" "%d,d,d")
38- (match_operand:DI 2 "arith_operand32" "d,P,N")))]
39+ [(set (match_operand:DI 0 "register_operand" "=d,d")
40+ (plus:DI (match_operand:DI 1 "register_operand" "%d,d")
41+ (match_operand:DI 2 "arith_operand" "d,i")))]
42 ""
43 "@
44 add\t%L0,%L1,%L2\;addc\t%M0,%M1,%M2
45- addi\t%L0,%L1,%2\;addc\t%M0,%M1,r0
46- addi\t%L0,%L1,%2\;addc\t%M0,%M1,r0\;addi\t%M0,%M0,-1"
47+ addi\t%L0,%L1,%j2\;addic\t%M0,%M1,%h2"
48 [(set_attr "type" "darith")
49 (set_attr "mode" "DI")
50- (set_attr "length" "8,8,12")])
51+ (set_attr "length" "8,8")])
52
53 ;;----------------------------------------------------------------
54 ;; Subtraction
Andrew Geissler84ad7c52020-06-27 00:00:16 -050055@@ -549,7 +548,7 @@
Brad Bishop286d45c2018-10-02 15:21:57 -040056 (define_insn "subdi3"
57 [(set (match_operand:DI 0 "register_operand" "=&d")
58 (minus:DI (match_operand:DI 1 "register_operand" "d")
59- (match_operand:DI 2 "arith_operand32" "d")))]
60+ (match_operand:DI 2 "register_operand" "d")))]
61 ""
62 "rsub\t%L0,%L2,%L1\;rsubc\t%M0,%M2,%M1"
63 [(set_attr "type" "darith")
64--
Andrew Geisslera9ff2b32020-10-16 10:11:54 -0500652.17.1
Brad Bishop286d45c2018-10-02 15:21:57 -040066