Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 1 | // Module Description ************************************************** |
| 2 | // |
| 3 | // Description: This module provides the implementation for the PRD Scan |
| 4 | // Comm Register Chip class. |
| 5 | // |
| 6 | // End Module Description ********************************************** |
| 7 | |
| 8 | //---------------------------------------------------------------------- |
| 9 | // Includes |
| 10 | //---------------------------------------------------------------------- |
| 11 | |
Zane Shelley | 52cb1a9 | 2019-08-21 14:38:31 -0500 | [diff] [blame] | 12 | #include <hei_includes.hpp> |
| 13 | #include <register/hei_hardware_register.hpp> |
| 14 | #include <util/hei_bit_string.hpp> |
| 15 | |
Zane Shelley | b77b573 | 2019-08-30 22:01:06 -0500 | [diff] [blame^] | 16 | #if 0 |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 17 | #include <iipchip.h> |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 18 | #include <prdfMain.H> |
| 19 | #include <prdfRasServices.H> |
| 20 | #include <prdfRegisterCache.H> |
| 21 | #include <prdfHomRegisterAccess.H> |
| 22 | #include <prdfPlatServices.H> |
| 23 | #include <prdfExtensibleChip.H> |
| 24 | |
| 25 | //---------------------------------------------------------------------- |
| 26 | // User Types |
| 27 | //---------------------------------------------------------------------- |
| 28 | |
| 29 | //---------------------------------------------------------------------- |
| 30 | // Constants |
| 31 | //---------------------------------------------------------------------- |
| 32 | |
| 33 | //---------------------------------------------------------------------- |
| 34 | // Macros |
| 35 | //---------------------------------------------------------------------- |
| 36 | |
| 37 | //---------------------------------------------------------------------- |
| 38 | // Internal Function Prototypes |
| 39 | //---------------------------------------------------------------------- |
| 40 | |
| 41 | //---------------------------------------------------------------------- |
| 42 | // Global Variables |
| 43 | //---------------------------------------------------------------------- |
| 44 | |
| 45 | //--------------------------------------------------------------------- |
| 46 | // Member Function Specifications |
| 47 | //--------------------------------------------------------------------- |
| 48 | |
| 49 | // -------------------------------------------------------------------- |
Zane Shelley | b77b573 | 2019-08-30 22:01:06 -0500 | [diff] [blame^] | 50 | #endif |
| 51 | |
Zane Shelley | 871adec | 2019-07-30 11:01:39 -0500 | [diff] [blame] | 52 | namespace libhei |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 53 | { |
| 54 | |
Zane Shelley | b77b573 | 2019-08-30 22:01:06 -0500 | [diff] [blame^] | 55 | #if 0 |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 56 | // --------------------------------------------------------------------- |
| 57 | |
Zane Shelley | cd36f43 | 2019-08-30 21:22:07 -0500 | [diff] [blame] | 58 | void HardwareRegister::SetBitString( const BitString *bs ) |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 59 | { |
| 60 | BitString & l_string = AccessBitString(); |
| 61 | l_string.setString(*bs); |
| 62 | } |
| 63 | |
| 64 | |
| 65 | //------------------------------------------------------------------------------ |
| 66 | |
Zane Shelley | cd36f43 | 2019-08-30 21:22:07 -0500 | [diff] [blame] | 67 | const BitString * HardwareRegister::GetBitString(ATTENTION_TYPE i_type) const |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 68 | { |
| 69 | // Calling Read() will ensure that an entry exists in the cache and the |
| 70 | // entry has at been synched with hardware at least once. Note that we |
| 71 | // cannot read hardware for write-only registers. In this case, an entry |
| 72 | // will be created in the cache, if it does not exist, when readCache() is |
| 73 | // called below. |
| 74 | if ( ( ACCESS_NONE != iv_operationType ) && |
| 75 | ( ACCESS_WO != iv_operationType ) ) |
| 76 | { |
| 77 | Read(); |
| 78 | } |
| 79 | return &(readCache()); |
| 80 | } |
| 81 | |
| 82 | //------------------------------------------------------------------------------ |
| 83 | |
Zane Shelley | cd36f43 | 2019-08-30 21:22:07 -0500 | [diff] [blame] | 84 | BitString & HardwareRegister::AccessBitString() |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 85 | { |
| 86 | // Calling Read() will ensure that an entry exists in the cache and the |
| 87 | // entry has at been synched with hardware at least once. Note that we |
| 88 | // cannot read hardware for write-only registers. In this case, an entry |
| 89 | // will be created in the cache, if it does not exist, when readCache() is |
| 90 | // called below. |
| 91 | if ( ( ACCESS_NONE != iv_operationType ) && |
| 92 | ( ACCESS_WO != iv_operationType ) ) |
| 93 | { |
| 94 | Read(); |
| 95 | } |
| 96 | |
| 97 | return readCache(); |
| 98 | } |
| 99 | |
| 100 | //------------------------------------------------------------------------------ |
| 101 | |
Zane Shelley | cd36f43 | 2019-08-30 21:22:07 -0500 | [diff] [blame] | 102 | uint32_t HardwareRegister::Read() const |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 103 | { |
| 104 | uint32_t o_rc = SUCCESS; |
| 105 | |
| 106 | // First query the cache for an existing entry. |
| 107 | if ( !queryCache() ) |
| 108 | { |
| 109 | // There was not a previous entry in the cache, so do a ForceRead() to |
| 110 | // sync the cache with hardware. |
| 111 | o_rc = ForceRead(); |
| 112 | } |
| 113 | |
| 114 | return o_rc; |
| 115 | } |
| 116 | |
| 117 | //------------------------------------------------------------------------------ |
| 118 | |
Zane Shelley | cd36f43 | 2019-08-30 21:22:07 -0500 | [diff] [blame] | 119 | uint32_t HardwareRegister::ForceRead() const |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 120 | { |
Zane Shelley | cd36f43 | 2019-08-30 21:22:07 -0500 | [diff] [blame] | 121 | #define PRDF_FUNC "[HardwareRegister::ForceRead] " |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 122 | |
| 123 | uint32_t o_rc = FAIL; |
| 124 | |
| 125 | do |
| 126 | { |
| 127 | // No read allowed if register access attribute is write-only or no |
| 128 | // access. |
| 129 | if ( ( ACCESS_NONE == iv_operationType ) && |
| 130 | ( ACCESS_WO == iv_operationType ) ) |
| 131 | { |
| 132 | PRDF_ERR( PRDF_FUNC "Write-only register: 0x%08x 0x%016llx", |
| 133 | getChip()->GetId(), iv_scomAddress ); |
| 134 | break; |
| 135 | } |
| 136 | |
| 137 | // Read hardware. |
Zane Shelley | ea1a1ac | 2019-08-08 16:27:20 -0500 | [diff] [blame] | 138 | o_rc = Access( readCache(), RegisterAccess::READ ); |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 139 | if ( SUCCESS != o_rc ) |
| 140 | { |
| 141 | // The read failed. Remove the entry from the cache so a subsequent |
| 142 | // Read() will attempt to read from hardware again. |
| 143 | flushCache( getChip() ); |
| 144 | } |
| 145 | |
| 146 | } while (0); |
| 147 | |
| 148 | return o_rc; |
| 149 | |
| 150 | #undef PRDF_FUNC |
| 151 | } |
| 152 | |
| 153 | //------------------------------------------------------------------------------ |
| 154 | |
Zane Shelley | cd36f43 | 2019-08-30 21:22:07 -0500 | [diff] [blame] | 155 | uint32_t HardwareRegister::Write() |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 156 | { |
Zane Shelley | cd36f43 | 2019-08-30 21:22:07 -0500 | [diff] [blame] | 157 | #define PRDF_FUNC "[HardwareRegister::Write] " |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 158 | |
| 159 | uint32_t o_rc = FAIL; |
| 160 | |
| 161 | do |
| 162 | { |
| 163 | // No write allowed if register access attribute is read-only or no |
| 164 | // access. |
| 165 | if ( ( ACCESS_NONE == iv_operationType ) && |
| 166 | ( ACCESS_RO == iv_operationType ) ) |
| 167 | { |
| 168 | PRDF_ERR( PRDF_FUNC "Read-only register: 0x%08x 0x%016llx", |
| 169 | getChip()->GetId(), iv_scomAddress ); |
| 170 | break; |
| 171 | } |
| 172 | |
| 173 | // Query the cache for an existing entry. |
| 174 | if ( !queryCache() ) |
| 175 | { |
| 176 | // Something bad happened and there was nothing in the cache to |
| 177 | // write to hardware. |
| 178 | PRDF_ERR( PRDF_FUNC "No entry found in cache: 0x%08x 0x%016llx", |
| 179 | getChip()->GetId(), iv_scomAddress ); |
| 180 | break; |
| 181 | } |
| 182 | |
| 183 | // Write hardware. |
Zane Shelley | ea1a1ac | 2019-08-08 16:27:20 -0500 | [diff] [blame] | 184 | o_rc = Access( readCache(), RegisterAccess::WRITE ); |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 185 | |
| 186 | } while (0); |
| 187 | |
| 188 | return o_rc; |
| 189 | |
| 190 | #undef PRDF_FUNC |
| 191 | } |
| 192 | |
| 193 | //------------------------------------------------------------------------------ |
| 194 | |
Zane Shelley | cd36f43 | 2019-08-30 21:22:07 -0500 | [diff] [blame] | 195 | uint32_t HardwareRegister::Access( BitString & bs, |
Zane Shelley | ea1a1ac | 2019-08-08 16:27:20 -0500 | [diff] [blame] | 196 | RegisterAccess::Operation op ) const |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 197 | { |
| 198 | int32_t l_rc = SCR_ACCESS_FAILED; |
| 199 | TARGETING::TargetHandle_t i_pchipTarget = getChip()->GetChipHandle(); |
| 200 | l_rc = getScomService().Access( i_pchipTarget,bs,iv_scomAddress,op ); |
| 201 | |
| 202 | return(l_rc); |
| 203 | } |
| 204 | //----------------------------------------------------------------------------- |
Zane Shelley | cd36f43 | 2019-08-30 21:22:07 -0500 | [diff] [blame] | 205 | ExtensibleChip* HardwareRegister::getChip( )const |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 206 | { |
| 207 | ExtensibleChip* l_pchip = NULL; |
| 208 | l_pchip = ServiceDataCollector::getChipAnalyzed(); |
| 209 | TARGETING::TYPE l_type = PlatServices::getTargetType( |
| 210 | l_pchip->GetChipHandle() ); |
| 211 | PRDF_ASSERT( iv_chipType == l_type ) |
| 212 | return l_pchip; |
| 213 | } |
| 214 | |
| 215 | //------------------------------------------------------------------------------ |
| 216 | |
Zane Shelley | cd36f43 | 2019-08-30 21:22:07 -0500 | [diff] [blame] | 217 | bool HardwareRegister::queryCache() const |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 218 | { |
| 219 | RegDataCache & cache = RegDataCache::getCachedRegisters(); |
| 220 | BitString * bs = cache.queryCache( getChip(), this ); |
| 221 | return ( NULL != bs ); |
| 222 | } |
| 223 | |
| 224 | //------------------------------------------------------------------------------ |
| 225 | |
Zane Shelley | cd36f43 | 2019-08-30 21:22:07 -0500 | [diff] [blame] | 226 | BitString & HardwareRegister::readCache() const |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 227 | { |
| 228 | RegDataCache & cache = RegDataCache::getCachedRegisters(); |
| 229 | return cache.read( getChip(), this ); |
| 230 | } |
| 231 | |
| 232 | //------------------------------------------------------------------------------ |
| 233 | |
Zane Shelley | cd36f43 | 2019-08-30 21:22:07 -0500 | [diff] [blame] | 234 | void HardwareRegister::flushCache( ExtensibleChip *i_pChip ) const |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 235 | { |
| 236 | RegDataCache & regDump = RegDataCache::getCachedRegisters(); |
| 237 | if( NULL == i_pChip ) |
| 238 | { |
| 239 | regDump.flush(); |
| 240 | } |
| 241 | else |
| 242 | { |
| 243 | regDump.flush( i_pChip ,this ); |
| 244 | } |
| 245 | } |
| 246 | |
| 247 | //----------------------------------------------------------------------------- |
| 248 | |
Zane Shelley | cd36f43 | 2019-08-30 21:22:07 -0500 | [diff] [blame] | 249 | bool HardwareRegister::operator == ( const HardwareRegister & i_rightRegister ) const |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 250 | { |
| 251 | if( iv_scomAddress == i_rightRegister.GetAddress() ) |
| 252 | { |
| 253 | return ( iv_chipType == i_rightRegister.getChipType() ); |
| 254 | } |
| 255 | else |
| 256 | { |
| 257 | return false ; |
| 258 | } |
| 259 | |
| 260 | } |
| 261 | |
| 262 | //----------------------------------------------------------------------------- |
Zane Shelley | cd36f43 | 2019-08-30 21:22:07 -0500 | [diff] [blame] | 263 | bool HardwareRegister::operator < ( const HardwareRegister & i_rightRegister ) const |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 264 | { |
| 265 | if( iv_scomAddress == i_rightRegister.GetAddress() ) |
| 266 | { |
| 267 | return ( iv_chipType < i_rightRegister.getChipType() ); |
| 268 | } |
| 269 | else |
| 270 | { |
| 271 | return( iv_scomAddress < i_rightRegister.GetAddress() ); |
| 272 | } |
| 273 | |
| 274 | |
| 275 | } |
| 276 | //----------------------------------------------------------------------------- |
Zane Shelley | cd36f43 | 2019-08-30 21:22:07 -0500 | [diff] [blame] | 277 | bool HardwareRegister::operator >= ( const HardwareRegister & i_rightRegister ) const |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 278 | { |
| 279 | return !( *this < i_rightRegister ); |
| 280 | } |
Zane Shelley | b77b573 | 2019-08-30 22:01:06 -0500 | [diff] [blame^] | 281 | #endif |
Zane Shelley | 871adec | 2019-07-30 11:01:39 -0500 | [diff] [blame] | 282 | |
| 283 | } // end namespace libhei |
| 284 | |