blob: c35422858ce599629a3f60b368ff533a2aedf5cb [file] [log] [blame]
Zane Shelleyfd3f9cc2019-07-29 15:02:24 -05001// Module Description **************************************************
2//
3// Description: This module provides the implementation for the PRD Scan
4// Comm Register Chip class.
5//
6// End Module Description **********************************************
7
8//----------------------------------------------------------------------
9// Includes
10//----------------------------------------------------------------------
11
Zane Shelley52cb1a92019-08-21 14:38:31 -050012#include <hei_includes.hpp>
13#include <register/hei_hardware_register.hpp>
14#include <util/hei_bit_string.hpp>
15
Zane Shelleyb77b5732019-08-30 22:01:06 -050016#if 0
Zane Shelleyfd3f9cc2019-07-29 15:02:24 -050017#include <iipchip.h>
Zane Shelleyfd3f9cc2019-07-29 15:02:24 -050018#include <prdfMain.H>
19#include <prdfRasServices.H>
20#include <prdfRegisterCache.H>
21#include <prdfHomRegisterAccess.H>
22#include <prdfPlatServices.H>
23#include <prdfExtensibleChip.H>
24
25//----------------------------------------------------------------------
26// User Types
27//----------------------------------------------------------------------
28
29//----------------------------------------------------------------------
30// Constants
31//----------------------------------------------------------------------
32
33//----------------------------------------------------------------------
34// Macros
35//----------------------------------------------------------------------
36
37//----------------------------------------------------------------------
38// Internal Function Prototypes
39//----------------------------------------------------------------------
40
41//----------------------------------------------------------------------
42// Global Variables
43//----------------------------------------------------------------------
44
45//---------------------------------------------------------------------
46// Member Function Specifications
47//---------------------------------------------------------------------
48
49// --------------------------------------------------------------------
Zane Shelleyb77b5732019-08-30 22:01:06 -050050#endif
51
Zane Shelley871adec2019-07-30 11:01:39 -050052namespace libhei
Zane Shelleyfd3f9cc2019-07-29 15:02:24 -050053{
54
Zane Shelleyb77b5732019-08-30 22:01:06 -050055#if 0
Zane Shelleyfd3f9cc2019-07-29 15:02:24 -050056// ---------------------------------------------------------------------
57
Zane Shelleycd36f432019-08-30 21:22:07 -050058void HardwareRegister::SetBitString( const BitString *bs )
Zane Shelleyfd3f9cc2019-07-29 15:02:24 -050059{
60 BitString & l_string = AccessBitString();
61 l_string.setString(*bs);
62}
63
64
65//------------------------------------------------------------------------------
66
Zane Shelleycd36f432019-08-30 21:22:07 -050067const BitString * HardwareRegister::GetBitString(ATTENTION_TYPE i_type) const
Zane Shelleyfd3f9cc2019-07-29 15:02:24 -050068{
69 // Calling Read() will ensure that an entry exists in the cache and the
70 // entry has at been synched with hardware at least once. Note that we
71 // cannot read hardware for write-only registers. In this case, an entry
72 // will be created in the cache, if it does not exist, when readCache() is
73 // called below.
74 if ( ( ACCESS_NONE != iv_operationType ) &&
75 ( ACCESS_WO != iv_operationType ) )
76 {
77 Read();
78 }
79 return &(readCache());
80}
81
82//------------------------------------------------------------------------------
83
Zane Shelleycd36f432019-08-30 21:22:07 -050084BitString & HardwareRegister::AccessBitString()
Zane Shelleyfd3f9cc2019-07-29 15:02:24 -050085{
86 // Calling Read() will ensure that an entry exists in the cache and the
87 // entry has at been synched with hardware at least once. Note that we
88 // cannot read hardware for write-only registers. In this case, an entry
89 // will be created in the cache, if it does not exist, when readCache() is
90 // called below.
91 if ( ( ACCESS_NONE != iv_operationType ) &&
92 ( ACCESS_WO != iv_operationType ) )
93 {
94 Read();
95 }
96
97 return readCache();
98}
99
100//------------------------------------------------------------------------------
101
Zane Shelleycd36f432019-08-30 21:22:07 -0500102uint32_t HardwareRegister::Read() const
Zane Shelleyfd3f9cc2019-07-29 15:02:24 -0500103{
104 uint32_t o_rc = SUCCESS;
105
106 // First query the cache for an existing entry.
107 if ( !queryCache() )
108 {
109 // There was not a previous entry in the cache, so do a ForceRead() to
110 // sync the cache with hardware.
111 o_rc = ForceRead();
112 }
113
114 return o_rc;
115}
116
117//------------------------------------------------------------------------------
118
Zane Shelleycd36f432019-08-30 21:22:07 -0500119uint32_t HardwareRegister::ForceRead() const
Zane Shelleyfd3f9cc2019-07-29 15:02:24 -0500120{
Zane Shelleycd36f432019-08-30 21:22:07 -0500121 #define PRDF_FUNC "[HardwareRegister::ForceRead] "
Zane Shelleyfd3f9cc2019-07-29 15:02:24 -0500122
123 uint32_t o_rc = FAIL;
124
125 do
126 {
127 // No read allowed if register access attribute is write-only or no
128 // access.
129 if ( ( ACCESS_NONE == iv_operationType ) &&
130 ( ACCESS_WO == iv_operationType ) )
131 {
132 PRDF_ERR( PRDF_FUNC "Write-only register: 0x%08x 0x%016llx",
133 getChip()->GetId(), iv_scomAddress );
134 break;
135 }
136
137 // Read hardware.
Zane Shelleyea1a1ac2019-08-08 16:27:20 -0500138 o_rc = Access( readCache(), RegisterAccess::READ );
Zane Shelleyfd3f9cc2019-07-29 15:02:24 -0500139 if ( SUCCESS != o_rc )
140 {
141 // The read failed. Remove the entry from the cache so a subsequent
142 // Read() will attempt to read from hardware again.
143 flushCache( getChip() );
144 }
145
146 } while (0);
147
148 return o_rc;
149
150 #undef PRDF_FUNC
151}
152
153//------------------------------------------------------------------------------
154
Zane Shelleycd36f432019-08-30 21:22:07 -0500155uint32_t HardwareRegister::Write()
Zane Shelleyfd3f9cc2019-07-29 15:02:24 -0500156{
Zane Shelleycd36f432019-08-30 21:22:07 -0500157 #define PRDF_FUNC "[HardwareRegister::Write] "
Zane Shelleyfd3f9cc2019-07-29 15:02:24 -0500158
159 uint32_t o_rc = FAIL;
160
161 do
162 {
163 // No write allowed if register access attribute is read-only or no
164 // access.
165 if ( ( ACCESS_NONE == iv_operationType ) &&
166 ( ACCESS_RO == iv_operationType ) )
167 {
168 PRDF_ERR( PRDF_FUNC "Read-only register: 0x%08x 0x%016llx",
169 getChip()->GetId(), iv_scomAddress );
170 break;
171 }
172
173 // Query the cache for an existing entry.
174 if ( !queryCache() )
175 {
176 // Something bad happened and there was nothing in the cache to
177 // write to hardware.
178 PRDF_ERR( PRDF_FUNC "No entry found in cache: 0x%08x 0x%016llx",
179 getChip()->GetId(), iv_scomAddress );
180 break;
181 }
182
183 // Write hardware.
Zane Shelleyea1a1ac2019-08-08 16:27:20 -0500184 o_rc = Access( readCache(), RegisterAccess::WRITE );
Zane Shelleyfd3f9cc2019-07-29 15:02:24 -0500185
186 } while (0);
187
188 return o_rc;
189
190 #undef PRDF_FUNC
191}
192
193//------------------------------------------------------------------------------
194
Zane Shelleycd36f432019-08-30 21:22:07 -0500195uint32_t HardwareRegister::Access( BitString & bs,
Zane Shelleyea1a1ac2019-08-08 16:27:20 -0500196 RegisterAccess::Operation op ) const
Zane Shelleyfd3f9cc2019-07-29 15:02:24 -0500197{
198 int32_t l_rc = SCR_ACCESS_FAILED;
199 TARGETING::TargetHandle_t i_pchipTarget = getChip()->GetChipHandle();
200 l_rc = getScomService().Access( i_pchipTarget,bs,iv_scomAddress,op );
201
202 return(l_rc);
203}
204//-----------------------------------------------------------------------------
Zane Shelleycd36f432019-08-30 21:22:07 -0500205ExtensibleChip* HardwareRegister::getChip( )const
Zane Shelleyfd3f9cc2019-07-29 15:02:24 -0500206{
207 ExtensibleChip* l_pchip = NULL;
208 l_pchip = ServiceDataCollector::getChipAnalyzed();
209 TARGETING::TYPE l_type = PlatServices::getTargetType(
210 l_pchip->GetChipHandle() );
211 PRDF_ASSERT( iv_chipType == l_type )
212 return l_pchip;
213}
214
215//------------------------------------------------------------------------------
216
Zane Shelleycd36f432019-08-30 21:22:07 -0500217bool HardwareRegister::queryCache() const
Zane Shelleyfd3f9cc2019-07-29 15:02:24 -0500218{
219 RegDataCache & cache = RegDataCache::getCachedRegisters();
220 BitString * bs = cache.queryCache( getChip(), this );
221 return ( NULL != bs );
222}
223
224//------------------------------------------------------------------------------
225
Zane Shelleycd36f432019-08-30 21:22:07 -0500226BitString & HardwareRegister::readCache() const
Zane Shelleyfd3f9cc2019-07-29 15:02:24 -0500227{
228 RegDataCache & cache = RegDataCache::getCachedRegisters();
229 return cache.read( getChip(), this );
230}
231
232//------------------------------------------------------------------------------
233
Zane Shelleycd36f432019-08-30 21:22:07 -0500234void HardwareRegister::flushCache( ExtensibleChip *i_pChip ) const
Zane Shelleyfd3f9cc2019-07-29 15:02:24 -0500235{
236 RegDataCache & regDump = RegDataCache::getCachedRegisters();
237 if( NULL == i_pChip )
238 {
239 regDump.flush();
240 }
241 else
242 {
243 regDump.flush( i_pChip ,this );
244 }
245}
246
247//-----------------------------------------------------------------------------
248
Zane Shelleycd36f432019-08-30 21:22:07 -0500249bool HardwareRegister::operator == ( const HardwareRegister & i_rightRegister ) const
Zane Shelleyfd3f9cc2019-07-29 15:02:24 -0500250{
251 if( iv_scomAddress == i_rightRegister.GetAddress() )
252 {
253 return ( iv_chipType == i_rightRegister.getChipType() );
254 }
255 else
256 {
257 return false ;
258 }
259
260}
261
262//-----------------------------------------------------------------------------
Zane Shelleycd36f432019-08-30 21:22:07 -0500263bool HardwareRegister::operator < ( const HardwareRegister & i_rightRegister ) const
Zane Shelleyfd3f9cc2019-07-29 15:02:24 -0500264{
265 if( iv_scomAddress == i_rightRegister.GetAddress() )
266 {
267 return ( iv_chipType < i_rightRegister.getChipType() );
268 }
269 else
270 {
271 return( iv_scomAddress < i_rightRegister.GetAddress() );
272 }
273
274
275}
276//-----------------------------------------------------------------------------
Zane Shelleycd36f432019-08-30 21:22:07 -0500277bool HardwareRegister::operator >= ( const HardwareRegister & i_rightRegister ) const
Zane Shelleyfd3f9cc2019-07-29 15:02:24 -0500278{
279 return !( *this < i_rightRegister );
280}
Zane Shelleyb77b5732019-08-30 22:01:06 -0500281#endif
Zane Shelley871adec2019-07-30 11:01:39 -0500282
283} // end namespace libhei
284