| Zane Shelley | 871adec | 2019-07-30 11:01:39 -0500 | [diff] [blame] | 1 | #pragma once | 
| Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 2 |  | 
| Zane Shelley | 52cb1a9 | 2019-08-21 14:38:31 -0500 | [diff] [blame] | 3 | #include <hei_includes.hpp> | 
|  | 4 | #include <register/hei_register.hpp> | 
|  | 5 | #include <util/hei_bit_string.hpp> | 
|  | 6 |  | 
| Zane Shelley | 871adec | 2019-07-30 11:01:39 -0500 | [diff] [blame] | 7 | namespace libhei | 
| Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 8 | { | 
|  | 9 |  | 
| Zane Shelley | 61565dc | 2019-09-18 21:57:10 -0500 | [diff] [blame] | 10 | /** | 
| Zane Shelley | 8deb090 | 2019-10-14 15:52:27 -0500 | [diff] [blame] | 11 | * @brief An abstract class containing information (e.g. address, type, length, | 
|  | 12 | *        etc.) for an actual hardware register. | 
| Zane Shelley | 61565dc | 2019-09-18 21:57:10 -0500 | [diff] [blame] | 13 | * | 
|  | 14 | * Hardware access: | 
|  | 15 | * | 
|  | 16 | *  Actual hardware access is defined by the user application via the user | 
|  | 17 | *  interface APIs. In order to tell the user application which chip to target, | 
| Zane Shelley | 53efc35 | 2019-10-03 21:46:39 -0500 | [diff] [blame] | 18 | *  the user application will give the isolator a list of pointers to its | 
|  | 19 | *  objects. They will then be passed into the public functions of this class | 
|  | 20 | *  and eventually given back to the user application when hardware access is | 
|  | 21 | *  needed. | 
| Zane Shelley | d0af358 | 2019-09-19 10:48:59 -0500 | [diff] [blame] | 22 | * | 
|  | 23 | * Register cache: | 
|  | 24 | * | 
|  | 25 | *  In order to save memory space, each instance of this class does not store | 
|  | 26 | *  the contents of the target hardware register. Instead, that data is stored | 
| Paul Greenwood | 6574f6e | 2019-09-17 09:43:22 -0500 | [diff] [blame] | 27 | *  in a register cache, which is a static variable defined in this class. This | 
| Zane Shelley | d0af358 | 2019-09-19 10:48:59 -0500 | [diff] [blame] | 28 | *  allows us to store only what we need. The cache can also be thought of as a | 
|  | 29 | *  snapshot of the registers at the time of isolation, which can be useful if | 
|  | 30 | *  the hardware is still running and register values could change. | 
|  | 31 | * | 
|  | 32 | *  In order to ensure stale data isn't used from the cache, call | 
|  | 33 | *  HardwareRegister::flushAll() before beginning isolation on a new attention. | 
|  | 34 | *  Also, HardwareRegister::flushAll() should be called when the isolator is | 
|  | 35 | *  uninitialized before the rest of the isolation objects are deleted. | 
| Zane Shelley | 61565dc | 2019-09-18 21:57:10 -0500 | [diff] [blame] | 36 | */ | 
| Zane Shelley | cd36f43 | 2019-08-30 21:22:07 -0500 | [diff] [blame] | 37 | class HardwareRegister : public Register | 
| Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 38 | { | 
|  | 39 | public: | 
| Zane Shelley | 8deb090 | 2019-10-14 15:52:27 -0500 | [diff] [blame] | 40 | /** @brief Pure virtual destructor. */ | 
|  | 41 | virtual ~HardwareRegister() = 0; | 
|  | 42 |  | 
|  | 43 | protected: | 
| Zane Shelley | 8deb090 | 2019-10-14 15:52:27 -0500 | [diff] [blame] | 44 | /** | 
|  | 45 | * @brief Constructor from components. | 
|  | 46 | * @param i_chipType    Type of chip associated with this register. | 
|  | 47 | * @param i_id          Unique ID for this register. | 
|  | 48 | * @param i_instance    Instance of this register | 
|  | 49 | * @param i_accessLevel Hardware access level for this register. | 
|  | 50 | */ | 
| Zane Shelley | 83da245 | 2019-10-25 15:45:34 -0500 | [diff] [blame] | 51 | HardwareRegister(ChipType_t i_chipType, RegisterId_t i_id, | 
|  | 52 | RegisterInstance_t i_instance, | 
|  | 53 | RegisterAccessLevel_t i_accessLevel) : | 
| Zane Shelley | 7f7a42d | 2019-10-28 13:28:31 -0500 | [diff] [blame] | 54 | Register(), | 
|  | 55 | iv_chipType(i_chipType), iv_id(i_id), iv_instance(i_instance), | 
|  | 56 | iv_accessLevel(i_accessLevel) | 
| Zane Shelley | 8deb090 | 2019-10-14 15:52:27 -0500 | [diff] [blame] | 57 | {} | 
|  | 58 |  | 
|  | 59 | private: // Instance variables | 
| Zane Shelley | 8deb090 | 2019-10-14 15:52:27 -0500 | [diff] [blame] | 60 | /** The type of chip associated with register. */ | 
|  | 61 | const ChipType_t iv_chipType; | 
|  | 62 |  | 
|  | 63 | /** The unique ID for this register. */ | 
|  | 64 | const RegisterId_t iv_id; | 
|  | 65 |  | 
|  | 66 | /** A register may have multiple instances. All of which will have the same | 
|  | 67 | *  ID. This variable is used to distinguish between each instance of the | 
|  | 68 | *  register. */ | 
|  | 69 | const RegisterInstance_t iv_instance; | 
|  | 70 |  | 
|  | 71 | /** The hardware access level of this register (read/write, read-only, | 
|  | 72 | *  write-only, etc.). */ | 
|  | 73 | const RegisterAccessLevel_t iv_accessLevel; | 
|  | 74 |  | 
|  | 75 | public: // Accessor functions | 
| Zane Shelley | 8deb090 | 2019-10-14 15:52:27 -0500 | [diff] [blame] | 76 | /** @return The type of chip associated with this register. */ | 
| Zane Shelley | 7f7a42d | 2019-10-28 13:28:31 -0500 | [diff] [blame] | 77 | ChipType_t getChipType() const | 
|  | 78 | { | 
|  | 79 | return iv_chipType; | 
|  | 80 | } | 
| Zane Shelley | 8deb090 | 2019-10-14 15:52:27 -0500 | [diff] [blame] | 81 |  | 
|  | 82 | /* @return The unique ID for this register. */ | 
| Zane Shelley | 7f7a42d | 2019-10-28 13:28:31 -0500 | [diff] [blame] | 83 | RegisterId_t getId() const | 
|  | 84 | { | 
|  | 85 | return iv_id; | 
|  | 86 | } | 
| Zane Shelley | 8deb090 | 2019-10-14 15:52:27 -0500 | [diff] [blame] | 87 |  | 
|  | 88 | /* @return The instance of this register. */ | 
| Zane Shelley | 7f7a42d | 2019-10-28 13:28:31 -0500 | [diff] [blame] | 89 | RegisterInstance_t getInstance() const | 
|  | 90 | { | 
|  | 91 | return iv_instance; | 
|  | 92 | } | 
| Zane Shelley | 8deb090 | 2019-10-14 15:52:27 -0500 | [diff] [blame] | 93 |  | 
|  | 94 | /** @return The hardware access level of this register. */ | 
| Zane Shelley | 7f7a42d | 2019-10-28 13:28:31 -0500 | [diff] [blame] | 95 | RegisterAccessLevel_t getAccessLevel() const | 
|  | 96 | { | 
|  | 97 | return iv_accessLevel; | 
|  | 98 | } | 
| Zane Shelley | 8deb090 | 2019-10-14 15:52:27 -0500 | [diff] [blame] | 99 |  | 
|  | 100 | // NOTE: The following are determined by child classes. | 
|  | 101 |  | 
|  | 102 | /** @return This register's type. */ | 
|  | 103 | virtual RegisterType_t getRegisterType() const = 0; | 
|  | 104 |  | 
|  | 105 | /** @return The address of this register. */ | 
|  | 106 | virtual RegisterAddress_t getAddress() const = 0; | 
|  | 107 |  | 
|  | 108 | /** @return The size (in bytes) of this register. */ | 
|  | 109 | virtual size_t getSize() const = 0; | 
|  | 110 |  | 
| Zane Shelley | 75e68e9 | 2019-10-18 16:16:23 -0500 | [diff] [blame] | 111 | public: // Operators | 
| Zane Shelley | 75e68e9 | 2019-10-18 16:16:23 -0500 | [diff] [blame] | 112 | /** @brief Equals operator. */ | 
| Zane Shelley | fe27b65 | 2019-10-28 11:33:07 -0500 | [diff] [blame] | 113 | bool operator==(const HardwareRegister& i_r) const | 
| Zane Shelley | 75e68e9 | 2019-10-18 16:16:23 -0500 | [diff] [blame] | 114 | { | 
|  | 115 | // Comparing register type, chip type, and address should be sufficient. | 
| Zane Shelley | 83da245 | 2019-10-25 15:45:34 -0500 | [diff] [blame] | 116 | return (getRegisterType() == i_r.getRegisterType()) && | 
| Zane Shelley | 7c8faa1 | 2019-10-28 22:26:28 -0500 | [diff] [blame] | 117 | (getChipType() == i_r.getChipType()) && | 
|  | 118 | (getAddress() == i_r.getAddress()); | 
| Zane Shelley | 75e68e9 | 2019-10-18 16:16:23 -0500 | [diff] [blame] | 119 | } | 
|  | 120 |  | 
|  | 121 | /** @brief Less than operator. */ | 
| Zane Shelley | fe27b65 | 2019-10-28 11:33:07 -0500 | [diff] [blame] | 122 | bool operator<(const HardwareRegister& i_r) const | 
| Zane Shelley | 75e68e9 | 2019-10-18 16:16:23 -0500 | [diff] [blame] | 123 | { | 
|  | 124 | // Comparing register type, chip type, and address should be sufficient. | 
| Zane Shelley | 83da245 | 2019-10-25 15:45:34 -0500 | [diff] [blame] | 125 | if (getRegisterType() < i_r.getRegisterType()) | 
| Zane Shelley | 75e68e9 | 2019-10-18 16:16:23 -0500 | [diff] [blame] | 126 | { | 
|  | 127 | return true; | 
|  | 128 | } | 
| Zane Shelley | 83da245 | 2019-10-25 15:45:34 -0500 | [diff] [blame] | 129 | else if (getRegisterType() == i_r.getRegisterType()) | 
| Zane Shelley | 75e68e9 | 2019-10-18 16:16:23 -0500 | [diff] [blame] | 130 | { | 
| Zane Shelley | 83da245 | 2019-10-25 15:45:34 -0500 | [diff] [blame] | 131 | if (getChipType() < i_r.getChipType()) | 
| Zane Shelley | 75e68e9 | 2019-10-18 16:16:23 -0500 | [diff] [blame] | 132 | { | 
|  | 133 | return true; | 
|  | 134 | } | 
| Zane Shelley | 83da245 | 2019-10-25 15:45:34 -0500 | [diff] [blame] | 135 | else if (getChipType() == i_r.getChipType()) | 
| Zane Shelley | 75e68e9 | 2019-10-18 16:16:23 -0500 | [diff] [blame] | 136 | { | 
| Zane Shelley | 83da245 | 2019-10-25 15:45:34 -0500 | [diff] [blame] | 137 | return (getAddress() < i_r.getAddress()); | 
| Zane Shelley | 75e68e9 | 2019-10-18 16:16:23 -0500 | [diff] [blame] | 138 | } | 
|  | 139 | } | 
|  | 140 |  | 
|  | 141 | return false; | 
|  | 142 | } | 
|  | 143 |  | 
| Zane Shelley | 8deb090 | 2019-10-14 15:52:27 -0500 | [diff] [blame] | 144 | public: | 
| Zane Shelley | 65ed96a | 2019-10-14 13:06:11 -0500 | [diff] [blame] | 145 | /** Function overloaded from parent Register class. */ | 
| Zane Shelley | fe27b65 | 2019-10-28 11:33:07 -0500 | [diff] [blame] | 146 | const BitString* getBitString(const Chip& i_chip) const; | 
| Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 147 |  | 
| Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 148 | /** | 
| Zane Shelley | 61565dc | 2019-09-18 21:57:10 -0500 | [diff] [blame] | 149 | * @brief  Reads a register from hardware via the user interface APIs. | 
| Zane Shelley | 53efc35 | 2019-10-03 21:46:39 -0500 | [diff] [blame] | 150 | * @param  i_chip  The target chip in which this register belongs. | 
| Zane Shelley | 61565dc | 2019-09-18 21:57:10 -0500 | [diff] [blame] | 151 | * @param  i_force When false, this function will only read from hardware if | 
|  | 152 | *                 an entry for this instance does not already exist in the | 
|  | 153 | *                 register cache. When true, the entry in the register | 
|  | 154 | *                 cache is flushed, if it exists. Then this function will | 
|  | 155 | *                 read from hardware and update the cache. | 
|  | 156 | * @return See the return code from the registerRead() user interface API. | 
| Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 157 | */ | 
| Zane Shelley | 2f4aa91 | 2020-05-08 14:28:18 -0500 | [diff] [blame] | 158 | bool read(const Chip& i_chip, bool i_force = false) const; | 
| Zane Shelley | 61565dc | 2019-09-18 21:57:10 -0500 | [diff] [blame] | 159 |  | 
| Zane Shelley | 83da245 | 2019-10-25 15:45:34 -0500 | [diff] [blame] | 160 | #ifndef __HEI_READ_ONLY | 
| Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 161 |  | 
|  | 162 | /** | 
| Zane Shelley | 61565dc | 2019-09-18 21:57:10 -0500 | [diff] [blame] | 163 | * @brief  Writes the value stored in the register cache to hardware via the | 
|  | 164 | *         user interface APIs. | 
| Zane Shelley | 53efc35 | 2019-10-03 21:46:39 -0500 | [diff] [blame] | 165 | * @param  i_chip  The target chip in which this register belongs. | 
| Zane Shelley | 61565dc | 2019-09-18 21:57:10 -0500 | [diff] [blame] | 166 | * @return See the return code from the registerWrite() user interface API. | 
| Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 167 | */ | 
| Zane Shelley | 2f4aa91 | 2020-05-08 14:28:18 -0500 | [diff] [blame] | 168 | bool write(const Chip& i_chip) const; | 
| Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 169 |  | 
| Zane Shelley | 83da245 | 2019-10-25 15:45:34 -0500 | [diff] [blame] | 170 | #endif // __HEI_READ_ONLY | 
| Zane Shelley | 61565dc | 2019-09-18 21:57:10 -0500 | [diff] [blame] | 171 |  | 
| Zane Shelley | afa669a | 2019-10-15 13:23:17 -0500 | [diff] [blame] | 172 | protected: | 
| Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 173 | /** | 
| Zane Shelley | afa669a | 2019-10-15 13:23:17 -0500 | [diff] [blame] | 174 | * @brief  Provides access to this register's BitString. | 
|  | 175 | * | 
|  | 176 | * WARNING: Allowing public access to this function may be dangerous. For | 
|  | 177 | *          now it should be left as protected. | 
|  | 178 | * | 
| Zane Shelley | 53efc35 | 2019-10-03 21:46:39 -0500 | [diff] [blame] | 179 | * @param  i_chip  The target chip in which this register belongs. | 
| Zane Shelley | afa669a | 2019-10-15 13:23:17 -0500 | [diff] [blame] | 180 | * @return A reference to the BitString. | 
| Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 181 | */ | 
| Zane Shelley | fe27b65 | 2019-10-28 11:33:07 -0500 | [diff] [blame] | 182 | BitString& accessBitString(const Chip& i_chip); | 
| Zane Shelley | 61565dc | 2019-09-18 21:57:10 -0500 | [diff] [blame] | 183 |  | 
| Zane Shelley | 61565dc | 2019-09-18 21:57:10 -0500 | [diff] [blame] | 184 | private: // Hardware accessor management functions. | 
| Zane Shelley | 53efc35 | 2019-10-03 21:46:39 -0500 | [diff] [blame] | 185 | /** @brief Asserts this register belongs on the target accessor chip. */ | 
| Zane Shelley | fe27b65 | 2019-10-28 11:33:07 -0500 | [diff] [blame] | 186 | void verifyAccessorChip(const Chip& i_chip) const | 
| Zane Shelley | 61565dc | 2019-09-18 21:57:10 -0500 | [diff] [blame] | 187 | { | 
| Zane Shelley | 83da245 | 2019-10-25 15:45:34 -0500 | [diff] [blame] | 188 | HEI_ASSERT(getChipType() == i_chip.getType()); | 
| Zane Shelley | 61565dc | 2019-09-18 21:57:10 -0500 | [diff] [blame] | 189 | } | 
| Zane Shelley | d0af358 | 2019-09-19 10:48:59 -0500 | [diff] [blame] | 190 |  | 
|  | 191 | private: // Register cache class variable | 
| Zane Shelley | d0af358 | 2019-09-19 10:48:59 -0500 | [diff] [blame] | 192 | /** | 
|  | 193 | * @brief Caches the contents of registers read from hardware. | 
|  | 194 | * | 
|  | 195 | * The goal is to create a snapshot of the hardware register contents as | 
|  | 196 | * close to the reported attention as possible. This snapshot is then used | 
|  | 197 | * for additional analysis/debug when needed. | 
|  | 198 | */ | 
|  | 199 | class Cache | 
|  | 200 | { | 
|  | 201 | public: | 
| Zane Shelley | d0af358 | 2019-09-19 10:48:59 -0500 | [diff] [blame] | 202 | /** @brief Default constructor. */ | 
|  | 203 | Cache() = default; | 
|  | 204 |  | 
|  | 205 | /** @brief Destructor. */ | 
|  | 206 | ~Cache() = default; | 
|  | 207 |  | 
|  | 208 | /** @brief Copy constructor. */ | 
| Zane Shelley | fe27b65 | 2019-10-28 11:33:07 -0500 | [diff] [blame] | 209 | Cache(const Cache&) = delete; | 
| Zane Shelley | d0af358 | 2019-09-19 10:48:59 -0500 | [diff] [blame] | 210 |  | 
|  | 211 | /** @brief Assignment operator. */ | 
| Zane Shelley | fe27b65 | 2019-10-28 11:33:07 -0500 | [diff] [blame] | 212 | Cache& operator=(const Cache&) = delete; | 
| Zane Shelley | d0af358 | 2019-09-19 10:48:59 -0500 | [diff] [blame] | 213 |  | 
|  | 214 | /** | 
|  | 215 | * @brief  Queries if a specific entry exists in the cache. | 
|  | 216 | * @param  i_chip  The target chip. | 
|  | 217 | * @param  i_hwReg The target register. | 
|  | 218 | * @return True if the entry exists, false otherwise. | 
|  | 219 | */ | 
| Zane Shelley | 7f7a42d | 2019-10-28 13:28:31 -0500 | [diff] [blame] | 220 | bool query(const Chip& i_chip, const HardwareRegister* i_hwReg) const; | 
| Zane Shelley | d0af358 | 2019-09-19 10:48:59 -0500 | [diff] [blame] | 221 |  | 
|  | 222 | /** | 
|  | 223 | * @brief  Returns the data buffer for the given chip and register. | 
|  | 224 | * @param  i_chip  The target chip. | 
|  | 225 | * @param  i_hwReg The target register. | 
|  | 226 | * @return A reference to the BitString containing the register data. | 
|  | 227 | * @note   If an entry does not exist in the cache, an entry will be | 
|  | 228 | *         created and the BitString will be initialized to 0. | 
|  | 229 | */ | 
| Zane Shelley | 7f7a42d | 2019-10-28 13:28:31 -0500 | [diff] [blame] | 230 | BitString& access(const Chip& i_chip, const HardwareRegister* i_hwReg); | 
| Zane Shelley | d0af358 | 2019-09-19 10:48:59 -0500 | [diff] [blame] | 231 |  | 
|  | 232 | /** @brief Flushes entire contents from cache. */ | 
|  | 233 | void flush(); | 
|  | 234 |  | 
|  | 235 | /** | 
|  | 236 | * @brief Removes a single register from the cache. | 
|  | 237 | * @param i_chip  The target chip. | 
|  | 238 | * @param i_hwReg The target register. | 
|  | 239 | */ | 
| Zane Shelley | fe27b65 | 2019-10-28 11:33:07 -0500 | [diff] [blame] | 240 | void flush(const Chip& i_chip, const HardwareRegister* i_hwReg); | 
| Zane Shelley | d0af358 | 2019-09-19 10:48:59 -0500 | [diff] [blame] | 241 |  | 
|  | 242 | private: | 
| Zane Shelley | d0af358 | 2019-09-19 10:48:59 -0500 | [diff] [blame] | 243 | /** | 
|  | 244 | * @brief Stores a BitStringBuffer for each HardwareRegister per Chip. | 
|  | 245 | * | 
|  | 246 | * The HardwareRegister keys will just be pointers to the isolation | 
|  | 247 | * objects created in the main initialize() API. Those should exist | 
|  | 248 | * until the main uninitialize() API is called. It is important that the | 
|  | 249 | * cache is flushed at the beginning of the uninitialize() API before | 
|  | 250 | * the rest of the isolation objects are deleted. | 
|  | 251 | * | 
|  | 252 | * The Chip keys are copies of the objects passed to the isolator | 
|  | 253 | * because the user application is responsible for storage of the | 
|  | 254 | * objects passed to the isolator. We don't want to chance a Chip was | 
|  | 255 | * created as a local variable that goes out of scope, or other similar | 
|  | 256 | * situations. | 
|  | 257 | */ | 
|  | 258 | std::map<Chip, std::map<const HardwareRegister*, BitString*>> iv_cache; | 
|  | 259 | }; | 
|  | 260 |  | 
|  | 261 | /** This allows all HardwareRegister objects access to the cache. */ | 
|  | 262 | static Cache cv_cache; | 
|  | 263 |  | 
|  | 264 | public: // Register cache management functions. | 
| Zane Shelley | d0af358 | 2019-09-19 10:48:59 -0500 | [diff] [blame] | 265 | /** @brief Flushes the entire register cache. */ | 
| Zane Shelley | 7f7a42d | 2019-10-28 13:28:31 -0500 | [diff] [blame] | 266 | static void flushAll() | 
|  | 267 | { | 
|  | 268 | cv_cache.flush(); | 
|  | 269 | } | 
| Zane Shelley | d0af358 | 2019-09-19 10:48:59 -0500 | [diff] [blame] | 270 |  | 
| Zane Shelley | 53efc35 | 2019-10-03 21:46:39 -0500 | [diff] [blame] | 271 | /** | 
|  | 272 | * @brief Flushes this register from the cache. | 
|  | 273 | * @param  i_chip  The target chip in which this register belongs. | 
|  | 274 | */ | 
| Zane Shelley | fe27b65 | 2019-10-28 11:33:07 -0500 | [diff] [blame] | 275 | void flush(const Chip& i_chip) const | 
| Zane Shelley | d0af358 | 2019-09-19 10:48:59 -0500 | [diff] [blame] | 276 | { | 
| Zane Shelley | 83da245 | 2019-10-25 15:45:34 -0500 | [diff] [blame] | 277 | cv_cache.flush(i_chip, this); | 
| Zane Shelley | d0af358 | 2019-09-19 10:48:59 -0500 | [diff] [blame] | 278 | } | 
|  | 279 |  | 
| Zane Shelley | 53efc35 | 2019-10-03 21:46:39 -0500 | [diff] [blame] | 280 | private: // Register cache management functions. | 
| Zane Shelley | 53efc35 | 2019-10-03 21:46:39 -0500 | [diff] [blame] | 281 | /** | 
|  | 282 | * @param  i_chip  The target chip in which this register belongs. | 
|  | 283 | * @return True if an entry for this register exist in this cache. | 
|  | 284 | */ | 
| Zane Shelley | fe27b65 | 2019-10-28 11:33:07 -0500 | [diff] [blame] | 285 | bool queryCache(const Chip& i_chip) const | 
| Zane Shelley | d0af358 | 2019-09-19 10:48:59 -0500 | [diff] [blame] | 286 | { | 
| Zane Shelley | 83da245 | 2019-10-25 15:45:34 -0500 | [diff] [blame] | 287 | return cv_cache.query(i_chip, this); | 
| Zane Shelley | 53efc35 | 2019-10-03 21:46:39 -0500 | [diff] [blame] | 288 | } | 
|  | 289 |  | 
|  | 290 | /** | 
|  | 291 | * @param  i_chip  The target chip in which this register belongs. | 
|  | 292 | * @return A reference to this register's BitString in cache. | 
|  | 293 | */ | 
| Zane Shelley | fe27b65 | 2019-10-28 11:33:07 -0500 | [diff] [blame] | 294 | BitString& accessCache(const Chip& i_chip) const | 
| Zane Shelley | 53efc35 | 2019-10-03 21:46:39 -0500 | [diff] [blame] | 295 | { | 
| Zane Shelley | 83da245 | 2019-10-25 15:45:34 -0500 | [diff] [blame] | 296 | return cv_cache.access(i_chip, this); | 
| Zane Shelley | d0af358 | 2019-09-19 10:48:59 -0500 | [diff] [blame] | 297 | } | 
| Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 298 | }; | 
|  | 299 |  | 
| Zane Shelley | 871adec | 2019-07-30 11:01:39 -0500 | [diff] [blame] | 300 | } // end namespace libhei |