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Zane Shelley871adec2019-07-30 11:01:39 -05001#pragma once
Zane Shelleyfd3f9cc2019-07-29 15:02:24 -05002
Zane Shelley52cb1a92019-08-21 14:38:31 -05003#include <register/hei_register.hpp>
Zane Shelley995be6c2021-02-24 15:48:55 -06004#include <util/hei_bit_string.hpp>
Zane Shelleyd5073512021-01-14 12:51:18 -06005#include <util/hei_includes.hpp>
Zane Shelley52cb1a92019-08-21 14:38:31 -05006
Zane Shelley871adec2019-07-30 11:01:39 -05007namespace libhei
Zane Shelleyfd3f9cc2019-07-29 15:02:24 -05008{
9
Zane Shelley61565dc2019-09-18 21:57:10 -050010/**
Zane Shelley8deb0902019-10-14 15:52:27 -050011 * @brief An abstract class containing information (e.g. address, type, length,
12 * etc.) for an actual hardware register.
Zane Shelley61565dc2019-09-18 21:57:10 -050013 *
14 * Hardware access:
15 *
16 * Actual hardware access is defined by the user application via the user
17 * interface APIs. In order to tell the user application which chip to target,
Zane Shelley53efc352019-10-03 21:46:39 -050018 * the user application will give the isolator a list of pointers to its
19 * objects. They will then be passed into the public functions of this class
20 * and eventually given back to the user application when hardware access is
21 * needed.
Zane Shelleyd0af3582019-09-19 10:48:59 -050022 *
23 * Register cache:
24 *
25 * In order to save memory space, each instance of this class does not store
26 * the contents of the target hardware register. Instead, that data is stored
Paul Greenwood6574f6e2019-09-17 09:43:22 -050027 * in a register cache, which is a static variable defined in this class. This
Zane Shelleyd0af3582019-09-19 10:48:59 -050028 * allows us to store only what we need. The cache can also be thought of as a
29 * snapshot of the registers at the time of isolation, which can be useful if
30 * the hardware is still running and register values could change.
31 *
32 * In order to ensure stale data isn't used from the cache, call
33 * HardwareRegister::flushAll() before beginning isolation on a new attention.
34 * Also, HardwareRegister::flushAll() should be called when the isolator is
35 * uninitialized before the rest of the isolation objects are deleted.
Zane Shelley61565dc2019-09-18 21:57:10 -050036 */
Zane Shelleycd36f432019-08-30 21:22:07 -050037class HardwareRegister : public Register
Zane Shelleyfd3f9cc2019-07-29 15:02:24 -050038{
Zane Shelley4de8ff82020-05-14 15:39:01 -050039 public: // Aliases
Patrick Williams2f7537d2023-05-10 07:51:39 -050040 using Ptr = std::shared_ptr<HardwareRegister>;
Zane Shelley4de8ff82020-05-14 15:39:01 -050041 using ConstPtr = std::shared_ptr<const HardwareRegister>;
42
43 using Key = std::pair<RegisterId_t, Instance_t>;
44
Zane Shelleyfd3f9cc2019-07-29 15:02:24 -050045 public:
Zane Shelley8deb0902019-10-14 15:52:27 -050046 /** @brief Pure virtual destructor. */
47 virtual ~HardwareRegister() = 0;
48
49 protected:
Zane Shelley8deb0902019-10-14 15:52:27 -050050 /**
51 * @brief Constructor from components.
Zane Shelley7667b712020-05-11 20:45:40 -050052 * @param i_id Unique ID for this register.
53 * @param i_instance Instance of this register
54 * @param i_flags Attribute flags for this register.
Zane Shelley8deb0902019-10-14 15:52:27 -050055 */
Zane Shelley5ec88102020-05-11 21:08:25 -050056 HardwareRegister(RegisterId_t i_id, Instance_t i_instance,
57 RegisterAttributeFlags_t i_flags) :
Patrick Williams8db65db2024-08-16 15:22:30 -040058 Register(), iv_id(i_id), iv_instance(i_instance), iv_flags(i_flags)
Zane Shelley8deb0902019-10-14 15:52:27 -050059 {}
60
61 private: // Instance variables
Zane Shelley8deb0902019-10-14 15:52:27 -050062 /** The unique ID for this register. */
63 const RegisterId_t iv_id;
64
65 /** A register may have multiple instances. All of which will have the same
66 * ID. This variable is used to distinguish between each instance of the
67 * register. */
Zane Shelley13b182b2020-05-07 20:23:45 -050068 const Instance_t iv_instance;
Zane Shelley8deb0902019-10-14 15:52:27 -050069
70 /** The hardware access level of this register (read/write, read-only,
71 * write-only, etc.). */
Zane Shelley7667b712020-05-11 20:45:40 -050072 const RegisterAttributeFlags_t iv_flags;
Zane Shelley8deb0902019-10-14 15:52:27 -050073
74 public: // Accessor functions
Zane Shelley8deb0902019-10-14 15:52:27 -050075 /* @return The unique ID for this register. */
Zane Shelley7f7a42d2019-10-28 13:28:31 -050076 RegisterId_t getId() const
77 {
78 return iv_id;
79 }
Zane Shelley8deb0902019-10-14 15:52:27 -050080
81 /* @return The instance of this register. */
Zane Shelley13b182b2020-05-07 20:23:45 -050082 Instance_t getInstance() const
Zane Shelley7f7a42d2019-10-28 13:28:31 -050083 {
84 return iv_instance;
85 }
Zane Shelley8deb0902019-10-14 15:52:27 -050086
Zane Shelley4de8ff82020-05-14 15:39:01 -050087 /** @return The register/instance key. */
88 Key getKey() const
89 {
90 return {iv_id, iv_instance};
91 }
92
Zane Shelley7667b712020-05-11 20:45:40 -050093 /** @return True if given flag is enabled, false if disabled. */
94 bool queryAttrFlag(RegisterAttributeFlags_t i_flag) const
Zane Shelley7f7a42d2019-10-28 13:28:31 -050095 {
Zane Shelley7667b712020-05-11 20:45:40 -050096 return (0 != (iv_flags & i_flag));
Zane Shelley7f7a42d2019-10-28 13:28:31 -050097 }
Zane Shelley8deb0902019-10-14 15:52:27 -050098
99 // NOTE: The following are determined by child classes.
100
101 /** @return This register's type. */
Zane Shelley5ec88102020-05-11 21:08:25 -0500102 virtual RegisterType_t getType() const = 0;
Zane Shelley8deb0902019-10-14 15:52:27 -0500103
104 /** @return The address of this register. */
105 virtual RegisterAddress_t getAddress() const = 0;
106
Zane Shelley75e68e92019-10-18 16:16:23 -0500107 public: // Operators
Zane Shelley75e68e92019-10-18 16:16:23 -0500108 /** @brief Equals operator. */
Zane Shelleyfe27b652019-10-28 11:33:07 -0500109 bool operator==(const HardwareRegister& i_r) const
Zane Shelley75e68e92019-10-18 16:16:23 -0500110 {
Zane Shelley981e56a2020-05-11 21:24:20 -0500111 // In general, comparing the ID and instance should be enough. However,
112 // no error will be thrown when adding the register to the flyweights
Zane Shelley4de8ff82020-05-14 15:39:01 -0500113 // and any other field differs. Therefore, all fields will be used and
Zane Shelley981e56a2020-05-11 21:24:20 -0500114 // invalid duplicates will be found when adding the register pointers
115 // to the IsolationChip objects.
116 return (getAddress() == i_r.getAddress()) && (getId() == i_r.getId()) &&
117 (getInstance() == i_r.getInstance()) &&
Zane Shelley4de8ff82020-05-14 15:39:01 -0500118 (getType() == i_r.getType()) && (iv_flags == i_r.iv_flags);
Zane Shelley75e68e92019-10-18 16:16:23 -0500119 }
120
121 /** @brief Less than operator. */
Zane Shelleyfe27b652019-10-28 11:33:07 -0500122 bool operator<(const HardwareRegister& i_r) const
Zane Shelley75e68e92019-10-18 16:16:23 -0500123 {
Zane Shelley981e56a2020-05-11 21:24:20 -0500124 // In general, comparing the ID and instance should be enough. However,
125 // no error will be thrown when adding the register to the flyweights
Zane Shelley4de8ff82020-05-14 15:39:01 -0500126 // and any other field differs. Therefore, all fields will be used and
Zane Shelley981e56a2020-05-11 21:24:20 -0500127 // invalid duplicates will be found when adding the register pointers
128 // to the IsolationChip objects.
Zane Shelley5ec88102020-05-11 21:08:25 -0500129 if (getAddress() < i_r.getAddress())
Zane Shelley75e68e92019-10-18 16:16:23 -0500130 {
131 return true;
132 }
Zane Shelley5ec88102020-05-11 21:08:25 -0500133 else if (getAddress() == i_r.getAddress())
Zane Shelley75e68e92019-10-18 16:16:23 -0500134 {
Zane Shelley981e56a2020-05-11 21:24:20 -0500135 if (getId() < i_r.getId())
136 {
137 return true;
138 }
139 else if (getId() == i_r.getId())
140 {
141 if (getInstance() < i_r.getInstance())
142 {
143 return true;
144 }
145 else if (getInstance() == i_r.getInstance())
146 {
Zane Shelley4de8ff82020-05-14 15:39:01 -0500147 if (getType() < i_r.getType())
148 {
149 return true;
150 }
151 else if (getType() == i_r.getType())
152 {
153 return (iv_flags < i_r.iv_flags);
154 }
Zane Shelley981e56a2020-05-11 21:24:20 -0500155 }
156 }
Zane Shelley75e68e92019-10-18 16:16:23 -0500157 }
158
159 return false;
160 }
161
Zane Shelley8deb0902019-10-14 15:52:27 -0500162 public:
Zane Shelley65ed96a2019-10-14 13:06:11 -0500163 /** Function overloaded from parent Register class. */
Zane Shelley5a78fa82022-09-16 16:49:58 -0500164 const BitString* getBitString(const Chip& i_chip) const override;
Zane Shelleyfd3f9cc2019-07-29 15:02:24 -0500165
Zane Shelleyfd3f9cc2019-07-29 15:02:24 -0500166 /**
Zane Shelley61565dc2019-09-18 21:57:10 -0500167 * @brief Reads a register from hardware via the user interface APIs.
Zane Shelley53efc352019-10-03 21:46:39 -0500168 * @param i_chip The target chip in which this register belongs.
Zane Shelley61565dc2019-09-18 21:57:10 -0500169 * @param i_force When false, this function will only read from hardware if
170 * an entry for this instance does not already exist in the
171 * register cache. When true, the entry in the register
172 * cache is flushed, if it exists. Then this function will
173 * read from hardware and update the cache.
174 * @return See the return code from the registerRead() user interface API.
Zane Shelleyfd3f9cc2019-07-29 15:02:24 -0500175 */
Zane Shelley2f4aa912020-05-08 14:28:18 -0500176 bool read(const Chip& i_chip, bool i_force = false) const;
Zane Shelley61565dc2019-09-18 21:57:10 -0500177
Ben Tyner7b3420b2020-05-11 10:52:07 -0500178#ifdef __HEI_ENABLE_HW_WRITE
Zane Shelleyfd3f9cc2019-07-29 15:02:24 -0500179
180 /**
Zane Shelley61565dc2019-09-18 21:57:10 -0500181 * @brief Writes the value stored in the register cache to hardware via the
182 * user interface APIs.
Zane Shelley53efc352019-10-03 21:46:39 -0500183 * @param i_chip The target chip in which this register belongs.
Zane Shelley61565dc2019-09-18 21:57:10 -0500184 * @return See the return code from the registerWrite() user interface API.
Zane Shelleyfd3f9cc2019-07-29 15:02:24 -0500185 */
Zane Shelley2f4aa912020-05-08 14:28:18 -0500186 bool write(const Chip& i_chip) const;
Zane Shelleyfd3f9cc2019-07-29 15:02:24 -0500187
Ben Tyner7b3420b2020-05-11 10:52:07 -0500188#endif // __HEI_ENABLE_HW_WRITE
Zane Shelley61565dc2019-09-18 21:57:10 -0500189
Caleb Palmere4ad4e32024-08-07 09:48:14 -0500190 /**
191 * @brief Sets the target position to 1 in the cached bit string.
192 * @param i_chip The target chip in which this register belongs.
193 * @param i_pos The target position.
194 */
195 void setBit(const Chip& i_chip, uint64_t i_pos) const;
196
197 /**
198 * @brief Sets the entire cached bit string to 1s.
199 * @param i_chip The target chip in which this register belongs.
200 */
201 void setAllBits(const Chip& i_chip) const;
202
203 /**
204 * @brief Sets the target position to 0 in the cached bit string.
205 * @param i_chip The target chip in which this register belongs.
206 * @param i_pos The target position.
207 */
208 void clearBit(const Chip& i_chip, uint64_t i_pos) const;
209
210 /**
211 * @brief Sets the entire cached bit string to 0s.
212 * @param i_chip The target chip in which this register belongs.
213 */
214 void clearAllBits(const Chip& i_chip) const;
215
Zane Shelleyafa669a2019-10-15 13:23:17 -0500216 protected:
Zane Shelleyfd3f9cc2019-07-29 15:02:24 -0500217 /**
Zane Shelleyafa669a2019-10-15 13:23:17 -0500218 * @brief Provides access to this register's BitString.
219 *
220 * WARNING: Allowing public access to this function may be dangerous. For
221 * now it should be left as protected.
222 *
Zane Shelley53efc352019-10-03 21:46:39 -0500223 * @param i_chip The target chip in which this register belongs.
Zane Shelleyafa669a2019-10-15 13:23:17 -0500224 * @return A reference to the BitString.
Zane Shelleyfd3f9cc2019-07-29 15:02:24 -0500225 */
Zane Shelleyfe27b652019-10-28 11:33:07 -0500226 BitString& accessBitString(const Chip& i_chip);
Zane Shelley61565dc2019-09-18 21:57:10 -0500227
Zane Shelleyd0af3582019-09-19 10:48:59 -0500228 private: // Register cache class variable
Zane Shelleyd0af3582019-09-19 10:48:59 -0500229 /**
230 * @brief Caches the contents of registers read from hardware.
231 *
232 * The goal is to create a snapshot of the hardware register contents as
233 * close to the reported attention as possible. This snapshot is then used
234 * for additional analysis/debug when needed.
235 */
236 class Cache
237 {
238 public:
Zane Shelleyd0af3582019-09-19 10:48:59 -0500239 /** @brief Default constructor. */
240 Cache() = default;
241
242 /** @brief Destructor. */
243 ~Cache() = default;
244
245 /** @brief Copy constructor. */
Zane Shelleyfe27b652019-10-28 11:33:07 -0500246 Cache(const Cache&) = delete;
Zane Shelleyd0af3582019-09-19 10:48:59 -0500247
248 /** @brief Assignment operator. */
Zane Shelleyfe27b652019-10-28 11:33:07 -0500249 Cache& operator=(const Cache&) = delete;
Zane Shelleyd0af3582019-09-19 10:48:59 -0500250
251 /**
252 * @brief Queries if a specific entry exists in the cache.
253 * @param i_chip The target chip.
254 * @param i_hwReg The target register.
255 * @return True if the entry exists, false otherwise.
256 */
Zane Shelley7f7a42d2019-10-28 13:28:31 -0500257 bool query(const Chip& i_chip, const HardwareRegister* i_hwReg) const;
Zane Shelleyd0af3582019-09-19 10:48:59 -0500258
259 /**
260 * @brief Returns the data buffer for the given chip and register.
261 * @param i_chip The target chip.
262 * @param i_hwReg The target register.
263 * @return A reference to the BitString containing the register data.
264 * @note If an entry does not exist in the cache, an entry will be
265 * created and the BitString will be initialized to 0.
266 */
Zane Shelley7f7a42d2019-10-28 13:28:31 -0500267 BitString& access(const Chip& i_chip, const HardwareRegister* i_hwReg);
Zane Shelleyd0af3582019-09-19 10:48:59 -0500268
269 /** @brief Flushes entire contents from cache. */
270 void flush();
271
272 /**
273 * @brief Removes a single register from the cache.
274 * @param i_chip The target chip.
275 * @param i_hwReg The target register.
276 */
Zane Shelleyfe27b652019-10-28 11:33:07 -0500277 void flush(const Chip& i_chip, const HardwareRegister* i_hwReg);
Zane Shelleyd0af3582019-09-19 10:48:59 -0500278
279 private:
Zane Shelleyd0af3582019-09-19 10:48:59 -0500280 /**
281 * @brief Stores a BitStringBuffer for each HardwareRegister per Chip.
282 *
283 * The HardwareRegister keys will just be pointers to the isolation
284 * objects created in the main initialize() API. Those should exist
285 * until the main uninitialize() API is called. It is important that the
286 * cache is flushed at the beginning of the uninitialize() API before
287 * the rest of the isolation objects are deleted.
288 *
289 * The Chip keys are copies of the objects passed to the isolator
290 * because the user application is responsible for storage of the
291 * objects passed to the isolator. We don't want to chance a Chip was
292 * created as a local variable that goes out of scope, or other similar
293 * situations.
294 */
295 std::map<Chip, std::map<const HardwareRegister*, BitString*>> iv_cache;
296 };
297
298 /** This allows all HardwareRegister objects access to the cache. */
299 static Cache cv_cache;
300
301 public: // Register cache management functions.
Zane Shelleyd0af3582019-09-19 10:48:59 -0500302 /** @brief Flushes the entire register cache. */
Zane Shelley7f7a42d2019-10-28 13:28:31 -0500303 static void flushAll()
304 {
305 cv_cache.flush();
306 }
Zane Shelleyd0af3582019-09-19 10:48:59 -0500307
Zane Shelley53efc352019-10-03 21:46:39 -0500308 /**
309 * @brief Flushes this register from the cache.
310 * @param i_chip The target chip in which this register belongs.
311 */
Zane Shelleyfe27b652019-10-28 11:33:07 -0500312 void flush(const Chip& i_chip) const
Zane Shelleyd0af3582019-09-19 10:48:59 -0500313 {
Zane Shelley83da2452019-10-25 15:45:34 -0500314 cv_cache.flush(i_chip, this);
Zane Shelleyd0af3582019-09-19 10:48:59 -0500315 }
316
Zane Shelley53efc352019-10-03 21:46:39 -0500317 private: // Register cache management functions.
Zane Shelley53efc352019-10-03 21:46:39 -0500318 /**
319 * @param i_chip The target chip in which this register belongs.
320 * @return True if an entry for this register exist in this cache.
321 */
Zane Shelleyfe27b652019-10-28 11:33:07 -0500322 bool queryCache(const Chip& i_chip) const
Zane Shelleyd0af3582019-09-19 10:48:59 -0500323 {
Zane Shelley83da2452019-10-25 15:45:34 -0500324 return cv_cache.query(i_chip, this);
Zane Shelley53efc352019-10-03 21:46:39 -0500325 }
326
327 /**
328 * @param i_chip The target chip in which this register belongs.
329 * @return A reference to this register's BitString in cache.
330 */
Zane Shelleyfe27b652019-10-28 11:33:07 -0500331 BitString& accessCache(const Chip& i_chip) const
Zane Shelley53efc352019-10-03 21:46:39 -0500332 {
Zane Shelley83da2452019-10-25 15:45:34 -0500333 return cv_cache.access(i_chip, this);
Zane Shelleyd0af3582019-09-19 10:48:59 -0500334 }
Zane Shelleyfd3f9cc2019-07-29 15:02:24 -0500335};
336
Zane Shelley871adec2019-07-30 11:01:39 -0500337} // end namespace libhei