Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 1 | // Module Description ************************************************** |
| 2 | // |
| 3 | // Description: This module provides the implementation for the PRD Scan |
| 4 | // Comm Register Chip class. |
| 5 | // |
| 6 | // End Module Description ********************************************** |
| 7 | |
| 8 | //---------------------------------------------------------------------- |
| 9 | // Includes |
| 10 | //---------------------------------------------------------------------- |
| 11 | |
Zane Shelley | 52cb1a9 | 2019-08-21 14:38:31 -0500 | [diff] [blame] | 12 | #include <hei_includes.hpp> |
Zane Shelley | 61565dc | 2019-09-18 21:57:10 -0500 | [diff] [blame] | 13 | #include <hei_user_interface.hpp> |
Zane Shelley | 52cb1a9 | 2019-08-21 14:38:31 -0500 | [diff] [blame] | 14 | #include <register/hei_hardware_register.hpp> |
| 15 | #include <util/hei_bit_string.hpp> |
| 16 | |
Zane Shelley | b77b573 | 2019-08-30 22:01:06 -0500 | [diff] [blame] | 17 | #if 0 |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 18 | #include <iipchip.h> |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 19 | #include <prdfMain.H> |
| 20 | #include <prdfRasServices.H> |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 21 | #include <prdfPlatServices.H> |
| 22 | #include <prdfExtensibleChip.H> |
| 23 | |
| 24 | //---------------------------------------------------------------------- |
| 25 | // User Types |
| 26 | //---------------------------------------------------------------------- |
| 27 | |
| 28 | //---------------------------------------------------------------------- |
| 29 | // Constants |
| 30 | //---------------------------------------------------------------------- |
| 31 | |
| 32 | //---------------------------------------------------------------------- |
| 33 | // Macros |
| 34 | //---------------------------------------------------------------------- |
| 35 | |
| 36 | //---------------------------------------------------------------------- |
| 37 | // Internal Function Prototypes |
| 38 | //---------------------------------------------------------------------- |
| 39 | |
| 40 | //---------------------------------------------------------------------- |
| 41 | // Global Variables |
| 42 | //---------------------------------------------------------------------- |
| 43 | |
| 44 | //--------------------------------------------------------------------- |
| 45 | // Member Function Specifications |
| 46 | //--------------------------------------------------------------------- |
| 47 | |
| 48 | // -------------------------------------------------------------------- |
Zane Shelley | b77b573 | 2019-08-30 22:01:06 -0500 | [diff] [blame] | 49 | #endif |
| 50 | |
Zane Shelley | 871adec | 2019-07-30 11:01:39 -0500 | [diff] [blame] | 51 | namespace libhei |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 52 | { |
| 53 | |
Zane Shelley | b77b573 | 2019-08-30 22:01:06 -0500 | [diff] [blame] | 54 | #if 0 |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 55 | // --------------------------------------------------------------------- |
| 56 | |
Zane Shelley | cd36f43 | 2019-08-30 21:22:07 -0500 | [diff] [blame] | 57 | void HardwareRegister::SetBitString( const BitString *bs ) |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 58 | { |
| 59 | BitString & l_string = AccessBitString(); |
| 60 | l_string.setString(*bs); |
| 61 | } |
| 62 | |
| 63 | |
| 64 | //------------------------------------------------------------------------------ |
| 65 | |
Zane Shelley | cd36f43 | 2019-08-30 21:22:07 -0500 | [diff] [blame] | 66 | const BitString * HardwareRegister::GetBitString(ATTENTION_TYPE i_type) const |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 67 | { |
| 68 | // Calling Read() will ensure that an entry exists in the cache and the |
| 69 | // entry has at been synched with hardware at least once. Note that we |
| 70 | // cannot read hardware for write-only registers. In this case, an entry |
Zane Shelley | d0af358 | 2019-09-19 10:48:59 -0500 | [diff] [blame] | 71 | // will be created in the cache, if it does not exist, when the cache is |
| 72 | // read below. |
| 73 | |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 74 | if ( ( ACCESS_NONE != iv_operationType ) && |
Zane Shelley | d0af358 | 2019-09-19 10:48:59 -0500 | [diff] [blame] | 75 | ( ACCESS_WO != iv_operationType ) ) |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 76 | { |
| 77 | Read(); |
| 78 | } |
Zane Shelley | d0af358 | 2019-09-19 10:48:59 -0500 | [diff] [blame] | 79 | |
| 80 | return &( accessCache() ); |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 81 | } |
| 82 | |
| 83 | //------------------------------------------------------------------------------ |
| 84 | |
Zane Shelley | cd36f43 | 2019-08-30 21:22:07 -0500 | [diff] [blame] | 85 | BitString & HardwareRegister::AccessBitString() |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 86 | { |
| 87 | // Calling Read() will ensure that an entry exists in the cache and the |
| 88 | // entry has at been synched with hardware at least once. Note that we |
| 89 | // cannot read hardware for write-only registers. In this case, an entry |
Zane Shelley | d0af358 | 2019-09-19 10:48:59 -0500 | [diff] [blame] | 90 | // will be created in the cache, if it does not exist, when the cache is |
| 91 | // read below. |
| 92 | |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 93 | if ( ( ACCESS_NONE != iv_operationType ) && |
Zane Shelley | d0af358 | 2019-09-19 10:48:59 -0500 | [diff] [blame] | 94 | ( ACCESS_WO != iv_operationType ) ) |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 95 | { |
| 96 | Read(); |
| 97 | } |
| 98 | |
Zane Shelley | d0af358 | 2019-09-19 10:48:59 -0500 | [diff] [blame] | 99 | return accessCache(); |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 100 | } |
Zane Shelley | 61565dc | 2019-09-18 21:57:10 -0500 | [diff] [blame] | 101 | #endif |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 102 | |
| 103 | //------------------------------------------------------------------------------ |
| 104 | |
Zane Shelley | 61565dc | 2019-09-18 21:57:10 -0500 | [diff] [blame] | 105 | ReturnCode HardwareRegister::read( bool i_force ) const |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 106 | { |
Zane Shelley | 61565dc | 2019-09-18 21:57:10 -0500 | [diff] [blame] | 107 | ReturnCode rc; |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 108 | |
Zane Shelley | 61565dc | 2019-09-18 21:57:10 -0500 | [diff] [blame] | 109 | // Read from hardware only if the read is forced or the entry for this |
| 110 | // instance does not exist in the cache. |
| 111 | if ( i_force || !queryCache() ) |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 112 | { |
Zane Shelley | d0af358 | 2019-09-19 10:48:59 -0500 | [diff] [blame] | 113 | #if 0 |
Zane Shelley | 61565dc | 2019-09-18 21:57:10 -0500 | [diff] [blame] | 114 | // This register must be readable. |
| 115 | HEI_ASSERT( ( ACCESS_NONE != iv_operationType ) && |
| 116 | ( ACCESS_WO != iv_operationType ) ); |
| 117 | |
| 118 | // Get the buffer from the register cache. |
Zane Shelley | d0af358 | 2019-09-19 10:48:59 -0500 | [diff] [blame] | 119 | BitString & bs = accessCache(); |
Zane Shelley | 61565dc | 2019-09-18 21:57:10 -0500 | [diff] [blame] | 120 | |
| 121 | // Get the byte size of the buffer. |
| 122 | size_t sz_buffer = BitString::getMinBytes( bs.getBitLen() ); |
| 123 | |
| 124 | // Read this register from hardware. |
| 125 | rc = registerRead( getAccessorChip().getChip(), bs.getBufAddr(), |
| 126 | sz_buffer, getRegisterType(), getAddress() ); |
Zane Shelley | d0af358 | 2019-09-19 10:48:59 -0500 | [diff] [blame] | 127 | #endif |
Zane Shelley | 61565dc | 2019-09-18 21:57:10 -0500 | [diff] [blame] | 128 | if ( RC_SUCCESS != rc ) |
| 129 | { |
| 130 | // The read failed and we can't trust what was put in the register |
| 131 | // cache. So remove this instance's entry from the cache. |
Zane Shelley | d0af358 | 2019-09-19 10:48:59 -0500 | [diff] [blame] | 132 | cv_cache.flush( getAccessorChip(), this ); |
Zane Shelley | 61565dc | 2019-09-18 21:57:10 -0500 | [diff] [blame] | 133 | } |
Zane Shelley | d0af358 | 2019-09-19 10:48:59 -0500 | [diff] [blame] | 134 | #if 0 |
Zane Shelley | 61565dc | 2019-09-18 21:57:10 -0500 | [diff] [blame] | 135 | else |
| 136 | { |
| 137 | // Sanity check. The returned size of the data written to the buffer |
| 138 | // should match the register size. |
| 139 | HEI_ASSERT( getSize() == sz_buffer ); |
| 140 | } |
Zane Shelley | 61565dc | 2019-09-18 21:57:10 -0500 | [diff] [blame] | 141 | #endif |
Zane Shelley | d0af358 | 2019-09-19 10:48:59 -0500 | [diff] [blame] | 142 | } |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 143 | |
Zane Shelley | 61565dc | 2019-09-18 21:57:10 -0500 | [diff] [blame] | 144 | return rc; |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 145 | } |
| 146 | |
| 147 | //------------------------------------------------------------------------------ |
| 148 | |
Zane Shelley | 61565dc | 2019-09-18 21:57:10 -0500 | [diff] [blame] | 149 | #ifndef __HEI_READ_ONLY |
| 150 | |
| 151 | ReturnCode HardwareRegister::write() const |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 152 | { |
Zane Shelley | 61565dc | 2019-09-18 21:57:10 -0500 | [diff] [blame] | 153 | ReturnCode rc; |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 154 | |
Zane Shelley | 61565dc | 2019-09-18 21:57:10 -0500 | [diff] [blame] | 155 | #if 0 |
| 156 | // This register must be writable. |
| 157 | HEI_ASSERT( ( ACCESS_NONE != iv_operationType ) && |
| 158 | ( ACCESS_RO != iv_operationType ) ); |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 159 | |
Zane Shelley | 61565dc | 2019-09-18 21:57:10 -0500 | [diff] [blame] | 160 | // An entry for this register must exist in the cache. |
| 161 | HEI_ASSERT( queryCache() ); |
| 162 | |
| 163 | // Get the buffer from the register cache. |
Zane Shelley | d0af358 | 2019-09-19 10:48:59 -0500 | [diff] [blame] | 164 | BitString & bs = accessCache(); |
Zane Shelley | 61565dc | 2019-09-18 21:57:10 -0500 | [diff] [blame] | 165 | |
| 166 | // Get the byte size of the buffer. |
| 167 | size_t sz_buffer = BitString::getMinBytes( bs.getBitLen() ); |
| 168 | |
| 169 | // Write to this register to hardware. |
| 170 | rc = registerWrite( getAccessorChip().getChip(), bs.getBufAddr(), |
| 171 | sz_buffer, getRegisterType(), getAddress() ); |
| 172 | |
| 173 | if ( RC_SUCCESS == rc ) |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 174 | { |
Zane Shelley | 61565dc | 2019-09-18 21:57:10 -0500 | [diff] [blame] | 175 | // Sanity check. The returned size of the data written to the buffer |
| 176 | // should match the register size. |
| 177 | HEI_ASSERT( getSize() == sz_buffer ); |
| 178 | } |
| 179 | #endif |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 180 | |
Zane Shelley | 61565dc | 2019-09-18 21:57:10 -0500 | [diff] [blame] | 181 | return rc; |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 182 | } |
| 183 | |
Zane Shelley | 61565dc | 2019-09-18 21:57:10 -0500 | [diff] [blame] | 184 | #endif // __HEI_READ_ONLY |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 185 | |
Zane Shelley | 61565dc | 2019-09-18 21:57:10 -0500 | [diff] [blame] | 186 | #if 0 |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 187 | //------------------------------------------------------------------------------ |
| 188 | |
Zane Shelley | cd36f43 | 2019-08-30 21:22:07 -0500 | [diff] [blame] | 189 | bool HardwareRegister::operator == ( const HardwareRegister & i_rightRegister ) const |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 190 | { |
| 191 | if( iv_scomAddress == i_rightRegister.GetAddress() ) |
| 192 | { |
| 193 | return ( iv_chipType == i_rightRegister.getChipType() ); |
| 194 | } |
| 195 | else |
| 196 | { |
| 197 | return false ; |
| 198 | } |
| 199 | |
| 200 | } |
| 201 | |
| 202 | //----------------------------------------------------------------------------- |
Zane Shelley | cd36f43 | 2019-08-30 21:22:07 -0500 | [diff] [blame] | 203 | bool HardwareRegister::operator < ( const HardwareRegister & i_rightRegister ) const |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 204 | { |
| 205 | if( iv_scomAddress == i_rightRegister.GetAddress() ) |
| 206 | { |
| 207 | return ( iv_chipType < i_rightRegister.getChipType() ); |
| 208 | } |
| 209 | else |
| 210 | { |
| 211 | return( iv_scomAddress < i_rightRegister.GetAddress() ); |
| 212 | } |
| 213 | |
| 214 | |
| 215 | } |
| 216 | //----------------------------------------------------------------------------- |
Zane Shelley | cd36f43 | 2019-08-30 21:22:07 -0500 | [diff] [blame] | 217 | bool HardwareRegister::operator >= ( const HardwareRegister & i_rightRegister ) const |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 218 | { |
| 219 | return !( *this < i_rightRegister ); |
| 220 | } |
Zane Shelley | b77b573 | 2019-08-30 22:01:06 -0500 | [diff] [blame] | 221 | #endif |
Zane Shelley | 871adec | 2019-07-30 11:01:39 -0500 | [diff] [blame] | 222 | |
Zane Shelley | 61565dc | 2019-09-18 21:57:10 -0500 | [diff] [blame] | 223 | //------------------------------------------------------------------------------ |
| 224 | |
| 225 | HardwareRegister::Accessor * HardwareRegister::cv_accessor = nullptr; |
| 226 | |
| 227 | //------------------------------------------------------------------------------ |
| 228 | |
Zane Shelley | d0af358 | 2019-09-19 10:48:59 -0500 | [diff] [blame] | 229 | HardwareRegister::Cache HardwareRegister::cv_cache {}; |
| 230 | |
| 231 | //------------------------------------------------------------------------------ |
| 232 | |
| 233 | bool HardwareRegister::Cache::query( const Chip & i_chip, |
| 234 | const HardwareRegister * i_hwReg ) const |
| 235 | { |
| 236 | // Does i_chip exist in the cache? |
| 237 | auto chipPairItr = iv_cache.find( i_chip ); |
| 238 | if ( iv_cache.end() != chipPairItr ) |
| 239 | { |
| 240 | auto & hwRegMap = chipPairItr->second; // for ease of use |
| 241 | |
| 242 | // Does i_hwReg exist in the cache? |
| 243 | auto hwRegPairItr = hwRegMap.find( i_hwReg ); |
| 244 | if ( hwRegMap.end() != hwRegPairItr ) |
| 245 | { |
| 246 | return true; |
| 247 | } |
| 248 | } |
| 249 | |
| 250 | return false; |
| 251 | } |
| 252 | |
| 253 | //------------------------------------------------------------------------------ |
| 254 | |
| 255 | BitString & HardwareRegister::Cache::access( const Chip & i_chip, |
| 256 | const HardwareRegister * i_hwReg ) |
| 257 | { |
| 258 | // If the entry does not exist, create a new entry. |
| 259 | if ( !query(i_chip, i_hwReg) ) |
| 260 | { |
| 261 | BitString * bs = new BitStringBuffer { i_hwReg->getByteSize() * 8 }; |
| 262 | iv_cache[i_chip][i_hwReg] = bs; |
| 263 | } |
| 264 | |
| 265 | // Return a reference to the target entry. |
| 266 | return *(iv_cache[i_chip][i_hwReg]); |
| 267 | } |
| 268 | |
| 269 | //------------------------------------------------------------------------------ |
| 270 | |
| 271 | void HardwareRegister::Cache::flush() |
| 272 | { |
| 273 | // Delete all of the BitStrings. |
| 274 | for ( auto & chipPair : iv_cache ) |
| 275 | { |
| 276 | for ( auto & hwRegPair : chipPair.second ) |
| 277 | { |
| 278 | delete hwRegPair.second; |
| 279 | } |
| 280 | } |
| 281 | |
| 282 | // !!! Do not delete the HardwareRegisters !!! |
| 283 | // Those are deleted when the main uninitialize() API is called. |
| 284 | |
| 285 | // Flush the rest of the cache. |
| 286 | iv_cache.clear(); |
| 287 | } |
| 288 | |
| 289 | //------------------------------------------------------------------------------ |
| 290 | |
| 291 | void HardwareRegister::Cache::flush( const Chip & i_chip, |
| 292 | const HardwareRegister * i_hwReg ) |
| 293 | { |
| 294 | // Does i_chip exist in the cache? |
| 295 | auto chipPairItr = iv_cache.find( i_chip ); |
| 296 | if ( iv_cache.end() != chipPairItr ) |
| 297 | { |
| 298 | auto & hwRegMap = chipPairItr->second; // for ease of use |
| 299 | |
| 300 | // Does i_hwReg exist in the cache? |
| 301 | auto hwRegPairItr = hwRegMap.find( i_hwReg ); |
| 302 | if ( hwRegMap.end() != hwRegPairItr ) |
| 303 | { |
| 304 | delete hwRegPairItr->second; // delete the BitString |
| 305 | hwRegMap.erase(i_hwReg); // remove the entry for this register |
| 306 | } |
| 307 | |
| 308 | // If i_hwReg was the only entry for i_chip, we can remove i_chip from |
| 309 | // the cache. |
| 310 | if ( hwRegMap.empty() ) |
| 311 | { |
| 312 | iv_cache.erase(i_chip); |
| 313 | } |
| 314 | } |
| 315 | } |
| 316 | |
| 317 | //------------------------------------------------------------------------------ |
| 318 | |
Zane Shelley | 871adec | 2019-07-30 11:01:39 -0500 | [diff] [blame] | 319 | } // end namespace libhei |
| 320 | |