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Zane Shelley52cb1a92019-08-21 14:38:31 -05001#include <hei_includes.hpp>
Zane Shelley61565dc2019-09-18 21:57:10 -05002#include <hei_user_interface.hpp>
Zane Shelley52cb1a92019-08-21 14:38:31 -05003#include <register/hei_hardware_register.hpp>
4#include <util/hei_bit_string.hpp>
5
Zane Shelley871adec2019-07-30 11:01:39 -05006namespace libhei
Zane Shelleyfd3f9cc2019-07-29 15:02:24 -05007{
8
Zane Shelley8deb0902019-10-14 15:52:27 -05009//------------------------------------------------------------------------------
Zane Shelleyfd3f9cc2019-07-29 15:02:24 -050010
Zane Shelley8deb0902019-10-14 15:52:27 -050011HardwareRegister::~HardwareRegister() {}
12
13//------------------------------------------------------------------------------
14
Zane Shelleyfe27b652019-10-28 11:33:07 -050015const BitString* HardwareRegister::getBitString(const Chip& i_chip) const
Zane Shelleyfd3f9cc2019-07-29 15:02:24 -050016{
Zane Shelley53efc352019-10-03 21:46:39 -050017 // Verify this register belongs on i_chip.
Zane Shelley83da2452019-10-25 15:45:34 -050018 verifyAccessorChip(i_chip);
Zane Shelley53efc352019-10-03 21:46:39 -050019
Paul Greenwood6574f6e2019-09-17 09:43:22 -050020 // Calling read() will ensure that an entry exists in the cache and the
Zane Shelleyfd3f9cc2019-07-29 15:02:24 -050021 // entry has at been synched with hardware at least once. Note that we
22 // cannot read hardware for write-only registers. In this case, an entry
Zane Shelleyd0af3582019-09-19 10:48:59 -050023 // will be created in the cache, if it does not exist, when the cache is
Zane Shelley53efc352019-10-03 21:46:39 -050024 // accessed below.
Zane Shelleyd0af3582019-09-19 10:48:59 -050025
Zane Shelley7c8faa12019-10-28 22:26:28 -050026 auto al = getAccessLevel();
27 if ((REG_ACCESS_NONE != al) && (REG_ACCESS_WO != al))
Zane Shelleyfd3f9cc2019-07-29 15:02:24 -050028 {
Zane Shelley83da2452019-10-25 15:45:34 -050029 read(i_chip);
Zane Shelleyfd3f9cc2019-07-29 15:02:24 -050030 }
Zane Shelleyd0af3582019-09-19 10:48:59 -050031
Zane Shelley83da2452019-10-25 15:45:34 -050032 return &(accessCache(i_chip));
Zane Shelleyfd3f9cc2019-07-29 15:02:24 -050033}
34
35//------------------------------------------------------------------------------
36
Zane Shelleyfe27b652019-10-28 11:33:07 -050037BitString& HardwareRegister::accessBitString(const Chip& i_chip)
Zane Shelleyfd3f9cc2019-07-29 15:02:24 -050038{
Zane Shelley53efc352019-10-03 21:46:39 -050039 // Verify this register belongs on i_chip.
Zane Shelley83da2452019-10-25 15:45:34 -050040 verifyAccessorChip(i_chip);
Zane Shelley53efc352019-10-03 21:46:39 -050041
Paul Greenwood6574f6e2019-09-17 09:43:22 -050042 // Calling read() will ensure that an entry exists in the cache and the
Zane Shelleyfd3f9cc2019-07-29 15:02:24 -050043 // entry has at been synched with hardware at least once. Note that we
44 // cannot read hardware for write-only registers. In this case, an entry
Zane Shelleyd0af3582019-09-19 10:48:59 -050045 // will be created in the cache, if it does not exist, when the cache is
Zane Shelley53efc352019-10-03 21:46:39 -050046 // accessed below.
Zane Shelleyd0af3582019-09-19 10:48:59 -050047
Zane Shelley7c8faa12019-10-28 22:26:28 -050048 auto al = getAccessLevel();
49 if ((REG_ACCESS_NONE != al) && (REG_ACCESS_WO != al))
Zane Shelleyfd3f9cc2019-07-29 15:02:24 -050050 {
Zane Shelley83da2452019-10-25 15:45:34 -050051 read(i_chip);
Zane Shelleyfd3f9cc2019-07-29 15:02:24 -050052 }
53
Zane Shelley83da2452019-10-25 15:45:34 -050054 return accessCache(i_chip);
Zane Shelleyfd3f9cc2019-07-29 15:02:24 -050055}
56
57//------------------------------------------------------------------------------
58
Zane Shelley2f4aa912020-05-08 14:28:18 -050059bool HardwareRegister::read(const Chip& i_chip, bool i_force) const
Zane Shelleyfd3f9cc2019-07-29 15:02:24 -050060{
Zane Shelley2f4aa912020-05-08 14:28:18 -050061 bool accessFailure = false;
Zane Shelleyfd3f9cc2019-07-29 15:02:24 -050062
Zane Shelley53efc352019-10-03 21:46:39 -050063 // Verify this register belongs on i_chip.
Zane Shelley83da2452019-10-25 15:45:34 -050064 verifyAccessorChip(i_chip);
Zane Shelley53efc352019-10-03 21:46:39 -050065
Zane Shelley61565dc2019-09-18 21:57:10 -050066 // Read from hardware only if the read is forced or the entry for this
67 // instance does not exist in the cache.
Zane Shelley83da2452019-10-25 15:45:34 -050068 if (i_force || !queryCache(i_chip))
Zane Shelleyfd3f9cc2019-07-29 15:02:24 -050069 {
Zane Shelley61565dc2019-09-18 21:57:10 -050070 // This register must be readable.
Zane Shelley7c8faa12019-10-28 22:26:28 -050071 auto al = getAccessLevel();
72 HEI_ASSERT((REG_ACCESS_NONE != al) && (REG_ACCESS_WO != al));
Zane Shelley61565dc2019-09-18 21:57:10 -050073
74 // Get the buffer from the register cache.
Zane Shelleyfe27b652019-10-28 11:33:07 -050075 BitString& bs = accessCache(i_chip);
Zane Shelley61565dc2019-09-18 21:57:10 -050076
77 // Get the byte size of the buffer.
Zane Shelley83da2452019-10-25 15:45:34 -050078 size_t sz_buffer = BitString::getMinBytes(bs.getBitLen());
Zane Shelley61565dc2019-09-18 21:57:10 -050079
80 // Read this register from hardware.
Zane Shelley2f4aa912020-05-08 14:28:18 -050081 accessFailure = registerRead(i_chip, bs.getBufAddr(), sz_buffer,
82 getRegisterType(), getAddress());
83 if (accessFailure)
Zane Shelley61565dc2019-09-18 21:57:10 -050084 {
85 // The read failed and we can't trust what was put in the register
86 // cache. So remove this instance's entry from the cache.
Zane Shelley83da2452019-10-25 15:45:34 -050087 flush(i_chip);
Zane Shelley61565dc2019-09-18 21:57:10 -050088 }
89 else
90 {
91 // Sanity check. The returned size of the data written to the buffer
92 // should match the register size.
Zane Shelley83da2452019-10-25 15:45:34 -050093 HEI_ASSERT(getSize() == sz_buffer);
Zane Shelley61565dc2019-09-18 21:57:10 -050094 }
Zane Shelleyd0af3582019-09-19 10:48:59 -050095 }
Zane Shelleyfd3f9cc2019-07-29 15:02:24 -050096
Zane Shelley2f4aa912020-05-08 14:28:18 -050097 return accessFailure;
Zane Shelleyfd3f9cc2019-07-29 15:02:24 -050098}
99
100//------------------------------------------------------------------------------
101
Zane Shelley61565dc2019-09-18 21:57:10 -0500102#ifndef __HEI_READ_ONLY
103
Zane Shelley2f4aa912020-05-08 14:28:18 -0500104bool HardwareRegister::write(const Chip& i_chip) const
Zane Shelleyfd3f9cc2019-07-29 15:02:24 -0500105{
Zane Shelley2f4aa912020-05-08 14:28:18 -0500106 bool accessFailure = false;
Zane Shelleyfd3f9cc2019-07-29 15:02:24 -0500107
Zane Shelley53efc352019-10-03 21:46:39 -0500108 // Verify this register belongs on i_chip.
Zane Shelley83da2452019-10-25 15:45:34 -0500109 verifyAccessorChip(i_chip);
Zane Shelley53efc352019-10-03 21:46:39 -0500110
Zane Shelley61565dc2019-09-18 21:57:10 -0500111 // This register must be writable.
Zane Shelley7c8faa12019-10-28 22:26:28 -0500112 auto al = getAccessLevel();
113 HEI_ASSERT((REG_ACCESS_NONE != al) && (REG_ACCESS_RO != al));
Zane Shelleyfd3f9cc2019-07-29 15:02:24 -0500114
Zane Shelley61565dc2019-09-18 21:57:10 -0500115 // An entry for this register must exist in the cache.
Zane Shelley83da2452019-10-25 15:45:34 -0500116 HEI_ASSERT(queryCache(i_chip));
Zane Shelley61565dc2019-09-18 21:57:10 -0500117
118 // Get the buffer from the register cache.
Zane Shelleyfe27b652019-10-28 11:33:07 -0500119 BitString& bs = accessCache(i_chip);
Zane Shelley61565dc2019-09-18 21:57:10 -0500120
121 // Get the byte size of the buffer.
Zane Shelley83da2452019-10-25 15:45:34 -0500122 size_t sz_buffer = BitString::getMinBytes(bs.getBitLen());
Zane Shelley61565dc2019-09-18 21:57:10 -0500123
124 // Write to this register to hardware.
Zane Shelley2f4aa912020-05-08 14:28:18 -0500125 accessFailure = registerWrite(i_chip, bs.getBufAddr(), sz_buffer,
126 getRegisterType(), getAddress());
Zane Shelley61565dc2019-09-18 21:57:10 -0500127
Zane Shelley2f4aa912020-05-08 14:28:18 -0500128 if (accessFailure)
Zane Shelleyfd3f9cc2019-07-29 15:02:24 -0500129 {
Zane Shelley61565dc2019-09-18 21:57:10 -0500130 // Sanity check. The returned size of the data written to the buffer
131 // should match the register size.
Zane Shelley83da2452019-10-25 15:45:34 -0500132 HEI_ASSERT(getSize() == sz_buffer);
Zane Shelley61565dc2019-09-18 21:57:10 -0500133 }
Zane Shelleyfd3f9cc2019-07-29 15:02:24 -0500134
Zane Shelley2f4aa912020-05-08 14:28:18 -0500135 return accessFailure;
Zane Shelleyfd3f9cc2019-07-29 15:02:24 -0500136}
137
Zane Shelley61565dc2019-09-18 21:57:10 -0500138#endif // __HEI_READ_ONLY
Zane Shelleyfd3f9cc2019-07-29 15:02:24 -0500139
Zane Shelleyfd3f9cc2019-07-29 15:02:24 -0500140//------------------------------------------------------------------------------
141
Zane Shelleyc4771992019-10-28 22:01:49 -0500142HardwareRegister::Cache HardwareRegister::cv_cache{};
Zane Shelleyd0af3582019-09-19 10:48:59 -0500143
144//------------------------------------------------------------------------------
145
Zane Shelleyfe27b652019-10-28 11:33:07 -0500146bool HardwareRegister::Cache::query(const Chip& i_chip,
147 const HardwareRegister* i_hwReg) const
Zane Shelleyd0af3582019-09-19 10:48:59 -0500148{
149 // Does i_chip exist in the cache?
Zane Shelley83da2452019-10-25 15:45:34 -0500150 auto chipPairItr = iv_cache.find(i_chip);
151 if (iv_cache.end() != chipPairItr)
Zane Shelleyd0af3582019-09-19 10:48:59 -0500152 {
Zane Shelleyfe27b652019-10-28 11:33:07 -0500153 auto& hwRegMap = chipPairItr->second; // for ease of use
Zane Shelleyd0af3582019-09-19 10:48:59 -0500154
155 // Does i_hwReg exist in the cache?
Zane Shelley83da2452019-10-25 15:45:34 -0500156 auto hwRegPairItr = hwRegMap.find(i_hwReg);
157 if (hwRegMap.end() != hwRegPairItr)
Zane Shelleyd0af3582019-09-19 10:48:59 -0500158 {
159 return true;
160 }
161 }
162
163 return false;
164}
165
166//------------------------------------------------------------------------------
167
Zane Shelleyfe27b652019-10-28 11:33:07 -0500168BitString& HardwareRegister::Cache::access(const Chip& i_chip,
Zane Shelleyc4771992019-10-28 22:01:49 -0500169 const HardwareRegister* i_hwReg)
Zane Shelleyd0af3582019-09-19 10:48:59 -0500170{
171 // If the entry does not exist, create a new entry.
Zane Shelley83da2452019-10-25 15:45:34 -0500172 if (!query(i_chip, i_hwReg))
Zane Shelleyd0af3582019-09-19 10:48:59 -0500173 {
Zane Shelleyc4771992019-10-28 22:01:49 -0500174 BitString* bs = new BitStringBuffer{i_hwReg->getSize() * 8};
Zane Shelley7c8faa12019-10-28 22:26:28 -0500175
Zane Shelleyd0af3582019-09-19 10:48:59 -0500176 iv_cache[i_chip][i_hwReg] = bs;
177 }
178
179 // Return a reference to the target entry.
180 return *(iv_cache[i_chip][i_hwReg]);
181}
182
183//------------------------------------------------------------------------------
184
185void HardwareRegister::Cache::flush()
186{
187 // Delete all of the BitStrings.
Zane Shelleyfe27b652019-10-28 11:33:07 -0500188 for (auto& chipPair : iv_cache)
Zane Shelleyd0af3582019-09-19 10:48:59 -0500189 {
Zane Shelleyfe27b652019-10-28 11:33:07 -0500190 for (auto& hwRegPair : chipPair.second)
Zane Shelleyd0af3582019-09-19 10:48:59 -0500191 {
192 delete hwRegPair.second;
193 }
194 }
195
196 // !!! Do not delete the HardwareRegisters !!!
197 // Those are deleted when the main uninitialize() API is called.
198
199 // Flush the rest of the cache.
200 iv_cache.clear();
201}
202
203//------------------------------------------------------------------------------
204
Zane Shelleyfe27b652019-10-28 11:33:07 -0500205void HardwareRegister::Cache::flush(const Chip& i_chip,
206 const HardwareRegister* i_hwReg)
Zane Shelleyd0af3582019-09-19 10:48:59 -0500207{
208 // Does i_chip exist in the cache?
Zane Shelley83da2452019-10-25 15:45:34 -0500209 auto chipPairItr = iv_cache.find(i_chip);
210 if (iv_cache.end() != chipPairItr)
Zane Shelleyd0af3582019-09-19 10:48:59 -0500211 {
Zane Shelleyfe27b652019-10-28 11:33:07 -0500212 auto& hwRegMap = chipPairItr->second; // for ease of use
Zane Shelleyd0af3582019-09-19 10:48:59 -0500213
214 // Does i_hwReg exist in the cache?
Zane Shelley83da2452019-10-25 15:45:34 -0500215 auto hwRegPairItr = hwRegMap.find(i_hwReg);
216 if (hwRegMap.end() != hwRegPairItr)
Zane Shelleyd0af3582019-09-19 10:48:59 -0500217 {
218 delete hwRegPairItr->second; // delete the BitString
219 hwRegMap.erase(i_hwReg); // remove the entry for this register
220 }
221
222 // If i_hwReg was the only entry for i_chip, we can remove i_chip from
223 // the cache.
Zane Shelley83da2452019-10-25 15:45:34 -0500224 if (hwRegMap.empty())
Zane Shelleyd0af3582019-09-19 10:48:59 -0500225 {
226 iv_cache.erase(i_chip);
227 }
228 }
229}
230
231//------------------------------------------------------------------------------
232
Zane Shelley871adec2019-07-30 11:01:39 -0500233} // end namespace libhei