Zane Shelley | 52cb1a9 | 2019-08-21 14:38:31 -0500 | [diff] [blame] | 1 | #include <hei_includes.hpp> |
Zane Shelley | 61565dc | 2019-09-18 21:57:10 -0500 | [diff] [blame] | 2 | #include <hei_user_interface.hpp> |
Zane Shelley | 52cb1a9 | 2019-08-21 14:38:31 -0500 | [diff] [blame] | 3 | #include <register/hei_hardware_register.hpp> |
| 4 | #include <util/hei_bit_string.hpp> |
| 5 | |
Zane Shelley | 871adec | 2019-07-30 11:01:39 -0500 | [diff] [blame] | 6 | namespace libhei |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 7 | { |
| 8 | |
Zane Shelley | 8deb090 | 2019-10-14 15:52:27 -0500 | [diff] [blame] | 9 | //------------------------------------------------------------------------------ |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 10 | |
Zane Shelley | 8deb090 | 2019-10-14 15:52:27 -0500 | [diff] [blame] | 11 | HardwareRegister::~HardwareRegister() {} |
| 12 | |
| 13 | //------------------------------------------------------------------------------ |
| 14 | |
| 15 | #if 0 |
Zane Shelley | 83da245 | 2019-10-25 15:45:34 -0500 | [diff] [blame] | 16 | void HardwareRegister::setBitString(const BitString *bs) |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 17 | { |
Zane Shelley | fe27b65 | 2019-10-28 11:33:07 -0500 | [diff] [blame] | 18 | BitString& l_string = accessBitString(); |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 19 | l_string.setString(*bs); |
| 20 | } |
Paul Greenwood | 6574f6e | 2019-09-17 09:43:22 -0500 | [diff] [blame] | 21 | #endif |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 22 | |
| 23 | //------------------------------------------------------------------------------ |
| 24 | |
Zane Shelley | fe27b65 | 2019-10-28 11:33:07 -0500 | [diff] [blame] | 25 | const BitString* HardwareRegister::getBitString(const Chip& i_chip) const |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 26 | { |
Zane Shelley | 53efc35 | 2019-10-03 21:46:39 -0500 | [diff] [blame] | 27 | // Verify this register belongs on i_chip. |
Zane Shelley | 83da245 | 2019-10-25 15:45:34 -0500 | [diff] [blame] | 28 | verifyAccessorChip(i_chip); |
Zane Shelley | 53efc35 | 2019-10-03 21:46:39 -0500 | [diff] [blame] | 29 | |
Paul Greenwood | 6574f6e | 2019-09-17 09:43:22 -0500 | [diff] [blame] | 30 | // Calling read() will ensure that an entry exists in the cache and the |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 31 | // entry has at been synched with hardware at least once. Note that we |
| 32 | // cannot read hardware for write-only registers. In this case, an entry |
Zane Shelley | d0af358 | 2019-09-19 10:48:59 -0500 | [diff] [blame] | 33 | // will be created in the cache, if it does not exist, when the cache is |
Zane Shelley | 53efc35 | 2019-10-03 21:46:39 -0500 | [diff] [blame] | 34 | // accessed below. |
Zane Shelley | d0af358 | 2019-09-19 10:48:59 -0500 | [diff] [blame] | 35 | |
Zane Shelley | 7c8faa1 | 2019-10-28 22:26:28 -0500 | [diff] [blame] | 36 | auto al = getAccessLevel(); |
| 37 | if ((REG_ACCESS_NONE != al) && (REG_ACCESS_WO != al)) |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 38 | { |
Zane Shelley | 83da245 | 2019-10-25 15:45:34 -0500 | [diff] [blame] | 39 | read(i_chip); |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 40 | } |
Zane Shelley | d0af358 | 2019-09-19 10:48:59 -0500 | [diff] [blame] | 41 | |
Zane Shelley | 83da245 | 2019-10-25 15:45:34 -0500 | [diff] [blame] | 42 | return &(accessCache(i_chip)); |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 43 | } |
| 44 | |
| 45 | //------------------------------------------------------------------------------ |
| 46 | |
Zane Shelley | fe27b65 | 2019-10-28 11:33:07 -0500 | [diff] [blame] | 47 | BitString& HardwareRegister::accessBitString(const Chip& i_chip) |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 48 | { |
Zane Shelley | 53efc35 | 2019-10-03 21:46:39 -0500 | [diff] [blame] | 49 | // Verify this register belongs on i_chip. |
Zane Shelley | 83da245 | 2019-10-25 15:45:34 -0500 | [diff] [blame] | 50 | verifyAccessorChip(i_chip); |
Zane Shelley | 53efc35 | 2019-10-03 21:46:39 -0500 | [diff] [blame] | 51 | |
Paul Greenwood | 6574f6e | 2019-09-17 09:43:22 -0500 | [diff] [blame] | 52 | // Calling read() will ensure that an entry exists in the cache and the |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 53 | // entry has at been synched with hardware at least once. Note that we |
| 54 | // cannot read hardware for write-only registers. In this case, an entry |
Zane Shelley | d0af358 | 2019-09-19 10:48:59 -0500 | [diff] [blame] | 55 | // will be created in the cache, if it does not exist, when the cache is |
Zane Shelley | 53efc35 | 2019-10-03 21:46:39 -0500 | [diff] [blame] | 56 | // accessed below. |
Zane Shelley | d0af358 | 2019-09-19 10:48:59 -0500 | [diff] [blame] | 57 | |
Zane Shelley | 7c8faa1 | 2019-10-28 22:26:28 -0500 | [diff] [blame] | 58 | auto al = getAccessLevel(); |
| 59 | if ((REG_ACCESS_NONE != al) && (REG_ACCESS_WO != al)) |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 60 | { |
Zane Shelley | 83da245 | 2019-10-25 15:45:34 -0500 | [diff] [blame] | 61 | read(i_chip); |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 62 | } |
| 63 | |
Zane Shelley | 83da245 | 2019-10-25 15:45:34 -0500 | [diff] [blame] | 64 | return accessCache(i_chip); |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 65 | } |
| 66 | |
| 67 | //------------------------------------------------------------------------------ |
| 68 | |
Zane Shelley | fe27b65 | 2019-10-28 11:33:07 -0500 | [diff] [blame] | 69 | ReturnCode HardwareRegister::read(const Chip& i_chip, bool i_force) const |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 70 | { |
Zane Shelley | 61565dc | 2019-09-18 21:57:10 -0500 | [diff] [blame] | 71 | ReturnCode rc; |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 72 | |
Zane Shelley | 53efc35 | 2019-10-03 21:46:39 -0500 | [diff] [blame] | 73 | // Verify this register belongs on i_chip. |
Zane Shelley | 83da245 | 2019-10-25 15:45:34 -0500 | [diff] [blame] | 74 | verifyAccessorChip(i_chip); |
Zane Shelley | 53efc35 | 2019-10-03 21:46:39 -0500 | [diff] [blame] | 75 | |
Zane Shelley | 61565dc | 2019-09-18 21:57:10 -0500 | [diff] [blame] | 76 | // Read from hardware only if the read is forced or the entry for this |
| 77 | // instance does not exist in the cache. |
Zane Shelley | 83da245 | 2019-10-25 15:45:34 -0500 | [diff] [blame] | 78 | if (i_force || !queryCache(i_chip)) |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 79 | { |
Zane Shelley | 61565dc | 2019-09-18 21:57:10 -0500 | [diff] [blame] | 80 | // This register must be readable. |
Zane Shelley | 7c8faa1 | 2019-10-28 22:26:28 -0500 | [diff] [blame] | 81 | auto al = getAccessLevel(); |
| 82 | HEI_ASSERT((REG_ACCESS_NONE != al) && (REG_ACCESS_WO != al)); |
Zane Shelley | 61565dc | 2019-09-18 21:57:10 -0500 | [diff] [blame] | 83 | |
| 84 | // Get the buffer from the register cache. |
Zane Shelley | fe27b65 | 2019-10-28 11:33:07 -0500 | [diff] [blame] | 85 | BitString& bs = accessCache(i_chip); |
Zane Shelley | 61565dc | 2019-09-18 21:57:10 -0500 | [diff] [blame] | 86 | |
| 87 | // Get the byte size of the buffer. |
Zane Shelley | 83da245 | 2019-10-25 15:45:34 -0500 | [diff] [blame] | 88 | size_t sz_buffer = BitString::getMinBytes(bs.getBitLen()); |
Zane Shelley | 61565dc | 2019-09-18 21:57:10 -0500 | [diff] [blame] | 89 | |
| 90 | // Read this register from hardware. |
Zane Shelley | 11b8994 | 2019-11-07 11:07:28 -0600 | [diff] [blame] | 91 | rc = registerRead(i_chip, bs.getBufAddr(), sz_buffer, getRegisterType(), |
| 92 | getAddress()); |
Zane Shelley | 83da245 | 2019-10-25 15:45:34 -0500 | [diff] [blame] | 93 | if (RC_SUCCESS != rc) |
Zane Shelley | 61565dc | 2019-09-18 21:57:10 -0500 | [diff] [blame] | 94 | { |
| 95 | // The read failed and we can't trust what was put in the register |
| 96 | // cache. So remove this instance's entry from the cache. |
Zane Shelley | 83da245 | 2019-10-25 15:45:34 -0500 | [diff] [blame] | 97 | flush(i_chip); |
Zane Shelley | 61565dc | 2019-09-18 21:57:10 -0500 | [diff] [blame] | 98 | } |
| 99 | else |
| 100 | { |
| 101 | // Sanity check. The returned size of the data written to the buffer |
| 102 | // should match the register size. |
Zane Shelley | 83da245 | 2019-10-25 15:45:34 -0500 | [diff] [blame] | 103 | HEI_ASSERT(getSize() == sz_buffer); |
Zane Shelley | 61565dc | 2019-09-18 21:57:10 -0500 | [diff] [blame] | 104 | } |
Zane Shelley | d0af358 | 2019-09-19 10:48:59 -0500 | [diff] [blame] | 105 | } |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 106 | |
Zane Shelley | 61565dc | 2019-09-18 21:57:10 -0500 | [diff] [blame] | 107 | return rc; |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 108 | } |
| 109 | |
| 110 | //------------------------------------------------------------------------------ |
| 111 | |
Zane Shelley | 61565dc | 2019-09-18 21:57:10 -0500 | [diff] [blame] | 112 | #ifndef __HEI_READ_ONLY |
| 113 | |
Zane Shelley | fe27b65 | 2019-10-28 11:33:07 -0500 | [diff] [blame] | 114 | ReturnCode HardwareRegister::write(const Chip& i_chip) const |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 115 | { |
Zane Shelley | 61565dc | 2019-09-18 21:57:10 -0500 | [diff] [blame] | 116 | ReturnCode rc; |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 117 | |
Zane Shelley | 53efc35 | 2019-10-03 21:46:39 -0500 | [diff] [blame] | 118 | // Verify this register belongs on i_chip. |
Zane Shelley | 83da245 | 2019-10-25 15:45:34 -0500 | [diff] [blame] | 119 | verifyAccessorChip(i_chip); |
Zane Shelley | 53efc35 | 2019-10-03 21:46:39 -0500 | [diff] [blame] | 120 | |
Zane Shelley | 61565dc | 2019-09-18 21:57:10 -0500 | [diff] [blame] | 121 | // This register must be writable. |
Zane Shelley | 7c8faa1 | 2019-10-28 22:26:28 -0500 | [diff] [blame] | 122 | auto al = getAccessLevel(); |
| 123 | HEI_ASSERT((REG_ACCESS_NONE != al) && (REG_ACCESS_RO != al)); |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 124 | |
Zane Shelley | 61565dc | 2019-09-18 21:57:10 -0500 | [diff] [blame] | 125 | // An entry for this register must exist in the cache. |
Zane Shelley | 83da245 | 2019-10-25 15:45:34 -0500 | [diff] [blame] | 126 | HEI_ASSERT(queryCache(i_chip)); |
Zane Shelley | 61565dc | 2019-09-18 21:57:10 -0500 | [diff] [blame] | 127 | |
| 128 | // Get the buffer from the register cache. |
Zane Shelley | fe27b65 | 2019-10-28 11:33:07 -0500 | [diff] [blame] | 129 | BitString& bs = accessCache(i_chip); |
Zane Shelley | 61565dc | 2019-09-18 21:57:10 -0500 | [diff] [blame] | 130 | |
| 131 | // Get the byte size of the buffer. |
Zane Shelley | 83da245 | 2019-10-25 15:45:34 -0500 | [diff] [blame] | 132 | size_t sz_buffer = BitString::getMinBytes(bs.getBitLen()); |
Zane Shelley | 61565dc | 2019-09-18 21:57:10 -0500 | [diff] [blame] | 133 | |
| 134 | // Write to this register to hardware. |
Zane Shelley | 11b8994 | 2019-11-07 11:07:28 -0600 | [diff] [blame] | 135 | rc = registerWrite(i_chip, bs.getBufAddr(), sz_buffer, getRegisterType(), |
| 136 | getAddress()); |
Zane Shelley | 61565dc | 2019-09-18 21:57:10 -0500 | [diff] [blame] | 137 | |
Zane Shelley | 83da245 | 2019-10-25 15:45:34 -0500 | [diff] [blame] | 138 | if (RC_SUCCESS == rc) |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 139 | { |
Zane Shelley | 61565dc | 2019-09-18 21:57:10 -0500 | [diff] [blame] | 140 | // Sanity check. The returned size of the data written to the buffer |
| 141 | // should match the register size. |
Zane Shelley | 83da245 | 2019-10-25 15:45:34 -0500 | [diff] [blame] | 142 | HEI_ASSERT(getSize() == sz_buffer); |
Zane Shelley | 61565dc | 2019-09-18 21:57:10 -0500 | [diff] [blame] | 143 | } |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 144 | |
Zane Shelley | 61565dc | 2019-09-18 21:57:10 -0500 | [diff] [blame] | 145 | return rc; |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 146 | } |
| 147 | |
Zane Shelley | 61565dc | 2019-09-18 21:57:10 -0500 | [diff] [blame] | 148 | #endif // __HEI_READ_ONLY |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 149 | |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 150 | //------------------------------------------------------------------------------ |
| 151 | |
Zane Shelley | c477199 | 2019-10-28 22:01:49 -0500 | [diff] [blame] | 152 | HardwareRegister::Cache HardwareRegister::cv_cache{}; |
Zane Shelley | d0af358 | 2019-09-19 10:48:59 -0500 | [diff] [blame] | 153 | |
| 154 | //------------------------------------------------------------------------------ |
| 155 | |
Zane Shelley | fe27b65 | 2019-10-28 11:33:07 -0500 | [diff] [blame] | 156 | bool HardwareRegister::Cache::query(const Chip& i_chip, |
| 157 | const HardwareRegister* i_hwReg) const |
Zane Shelley | d0af358 | 2019-09-19 10:48:59 -0500 | [diff] [blame] | 158 | { |
| 159 | // Does i_chip exist in the cache? |
Zane Shelley | 83da245 | 2019-10-25 15:45:34 -0500 | [diff] [blame] | 160 | auto chipPairItr = iv_cache.find(i_chip); |
| 161 | if (iv_cache.end() != chipPairItr) |
Zane Shelley | d0af358 | 2019-09-19 10:48:59 -0500 | [diff] [blame] | 162 | { |
Zane Shelley | fe27b65 | 2019-10-28 11:33:07 -0500 | [diff] [blame] | 163 | auto& hwRegMap = chipPairItr->second; // for ease of use |
Zane Shelley | d0af358 | 2019-09-19 10:48:59 -0500 | [diff] [blame] | 164 | |
| 165 | // Does i_hwReg exist in the cache? |
Zane Shelley | 83da245 | 2019-10-25 15:45:34 -0500 | [diff] [blame] | 166 | auto hwRegPairItr = hwRegMap.find(i_hwReg); |
| 167 | if (hwRegMap.end() != hwRegPairItr) |
Zane Shelley | d0af358 | 2019-09-19 10:48:59 -0500 | [diff] [blame] | 168 | { |
| 169 | return true; |
| 170 | } |
| 171 | } |
| 172 | |
| 173 | return false; |
| 174 | } |
| 175 | |
| 176 | //------------------------------------------------------------------------------ |
| 177 | |
Zane Shelley | fe27b65 | 2019-10-28 11:33:07 -0500 | [diff] [blame] | 178 | BitString& HardwareRegister::Cache::access(const Chip& i_chip, |
Zane Shelley | c477199 | 2019-10-28 22:01:49 -0500 | [diff] [blame] | 179 | const HardwareRegister* i_hwReg) |
Zane Shelley | d0af358 | 2019-09-19 10:48:59 -0500 | [diff] [blame] | 180 | { |
| 181 | // If the entry does not exist, create a new entry. |
Zane Shelley | 83da245 | 2019-10-25 15:45:34 -0500 | [diff] [blame] | 182 | if (!query(i_chip, i_hwReg)) |
Zane Shelley | d0af358 | 2019-09-19 10:48:59 -0500 | [diff] [blame] | 183 | { |
Zane Shelley | c477199 | 2019-10-28 22:01:49 -0500 | [diff] [blame] | 184 | BitString* bs = new BitStringBuffer{i_hwReg->getSize() * 8}; |
Zane Shelley | 7c8faa1 | 2019-10-28 22:26:28 -0500 | [diff] [blame] | 185 | |
Zane Shelley | d0af358 | 2019-09-19 10:48:59 -0500 | [diff] [blame] | 186 | iv_cache[i_chip][i_hwReg] = bs; |
| 187 | } |
| 188 | |
| 189 | // Return a reference to the target entry. |
| 190 | return *(iv_cache[i_chip][i_hwReg]); |
| 191 | } |
| 192 | |
| 193 | //------------------------------------------------------------------------------ |
| 194 | |
| 195 | void HardwareRegister::Cache::flush() |
| 196 | { |
| 197 | // Delete all of the BitStrings. |
Zane Shelley | fe27b65 | 2019-10-28 11:33:07 -0500 | [diff] [blame] | 198 | for (auto& chipPair : iv_cache) |
Zane Shelley | d0af358 | 2019-09-19 10:48:59 -0500 | [diff] [blame] | 199 | { |
Zane Shelley | fe27b65 | 2019-10-28 11:33:07 -0500 | [diff] [blame] | 200 | for (auto& hwRegPair : chipPair.second) |
Zane Shelley | d0af358 | 2019-09-19 10:48:59 -0500 | [diff] [blame] | 201 | { |
| 202 | delete hwRegPair.second; |
| 203 | } |
| 204 | } |
| 205 | |
| 206 | // !!! Do not delete the HardwareRegisters !!! |
| 207 | // Those are deleted when the main uninitialize() API is called. |
| 208 | |
| 209 | // Flush the rest of the cache. |
| 210 | iv_cache.clear(); |
| 211 | } |
| 212 | |
| 213 | //------------------------------------------------------------------------------ |
| 214 | |
Zane Shelley | fe27b65 | 2019-10-28 11:33:07 -0500 | [diff] [blame] | 215 | void HardwareRegister::Cache::flush(const Chip& i_chip, |
| 216 | const HardwareRegister* i_hwReg) |
Zane Shelley | d0af358 | 2019-09-19 10:48:59 -0500 | [diff] [blame] | 217 | { |
| 218 | // Does i_chip exist in the cache? |
Zane Shelley | 83da245 | 2019-10-25 15:45:34 -0500 | [diff] [blame] | 219 | auto chipPairItr = iv_cache.find(i_chip); |
| 220 | if (iv_cache.end() != chipPairItr) |
Zane Shelley | d0af358 | 2019-09-19 10:48:59 -0500 | [diff] [blame] | 221 | { |
Zane Shelley | fe27b65 | 2019-10-28 11:33:07 -0500 | [diff] [blame] | 222 | auto& hwRegMap = chipPairItr->second; // for ease of use |
Zane Shelley | d0af358 | 2019-09-19 10:48:59 -0500 | [diff] [blame] | 223 | |
| 224 | // Does i_hwReg exist in the cache? |
Zane Shelley | 83da245 | 2019-10-25 15:45:34 -0500 | [diff] [blame] | 225 | auto hwRegPairItr = hwRegMap.find(i_hwReg); |
| 226 | if (hwRegMap.end() != hwRegPairItr) |
Zane Shelley | d0af358 | 2019-09-19 10:48:59 -0500 | [diff] [blame] | 227 | { |
| 228 | delete hwRegPairItr->second; // delete the BitString |
| 229 | hwRegMap.erase(i_hwReg); // remove the entry for this register |
| 230 | } |
| 231 | |
| 232 | // If i_hwReg was the only entry for i_chip, we can remove i_chip from |
| 233 | // the cache. |
Zane Shelley | 83da245 | 2019-10-25 15:45:34 -0500 | [diff] [blame] | 234 | if (hwRegMap.empty()) |
Zane Shelley | d0af358 | 2019-09-19 10:48:59 -0500 | [diff] [blame] | 235 | { |
| 236 | iv_cache.erase(i_chip); |
| 237 | } |
| 238 | } |
| 239 | } |
| 240 | |
| 241 | //------------------------------------------------------------------------------ |
| 242 | |
Zane Shelley | 871adec | 2019-07-30 11:01:39 -0500 | [diff] [blame] | 243 | } // end namespace libhei |