Zane Shelley | 52cb1a9 | 2019-08-21 14:38:31 -0500 | [diff] [blame] | 1 | #include <hei_includes.hpp> |
Zane Shelley | 61565dc | 2019-09-18 21:57:10 -0500 | [diff] [blame] | 2 | #include <hei_user_interface.hpp> |
Zane Shelley | 52cb1a9 | 2019-08-21 14:38:31 -0500 | [diff] [blame] | 3 | #include <register/hei_hardware_register.hpp> |
| 4 | #include <util/hei_bit_string.hpp> |
| 5 | |
Zane Shelley | 871adec | 2019-07-30 11:01:39 -0500 | [diff] [blame] | 6 | namespace libhei |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 7 | { |
| 8 | |
Zane Shelley | 8deb090 | 2019-10-14 15:52:27 -0500 | [diff] [blame] | 9 | //------------------------------------------------------------------------------ |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 10 | |
Zane Shelley | 8deb090 | 2019-10-14 15:52:27 -0500 | [diff] [blame] | 11 | HardwareRegister::~HardwareRegister() {} |
| 12 | |
| 13 | //------------------------------------------------------------------------------ |
| 14 | |
Zane Shelley | fe27b65 | 2019-10-28 11:33:07 -0500 | [diff] [blame] | 15 | const BitString* HardwareRegister::getBitString(const Chip& i_chip) const |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 16 | { |
Zane Shelley | 53efc35 | 2019-10-03 21:46:39 -0500 | [diff] [blame] | 17 | // Verify this register belongs on i_chip. |
Zane Shelley | 83da245 | 2019-10-25 15:45:34 -0500 | [diff] [blame] | 18 | verifyAccessorChip(i_chip); |
Zane Shelley | 53efc35 | 2019-10-03 21:46:39 -0500 | [diff] [blame] | 19 | |
Paul Greenwood | 6574f6e | 2019-09-17 09:43:22 -0500 | [diff] [blame] | 20 | // Calling read() will ensure that an entry exists in the cache and the |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 21 | // entry has at been synched with hardware at least once. Note that we |
| 22 | // cannot read hardware for write-only registers. In this case, an entry |
Zane Shelley | d0af358 | 2019-09-19 10:48:59 -0500 | [diff] [blame] | 23 | // will be created in the cache, if it does not exist, when the cache is |
Zane Shelley | 53efc35 | 2019-10-03 21:46:39 -0500 | [diff] [blame] | 24 | // accessed below. |
Zane Shelley | d0af358 | 2019-09-19 10:48:59 -0500 | [diff] [blame] | 25 | |
Zane Shelley | 7667b71 | 2020-05-11 20:45:40 -0500 | [diff] [blame^] | 26 | if (queryAttrFlag(REG_ATTR_ACCESS_READ)) |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 27 | { |
Zane Shelley | 83da245 | 2019-10-25 15:45:34 -0500 | [diff] [blame] | 28 | read(i_chip); |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 29 | } |
Zane Shelley | d0af358 | 2019-09-19 10:48:59 -0500 | [diff] [blame] | 30 | |
Zane Shelley | 83da245 | 2019-10-25 15:45:34 -0500 | [diff] [blame] | 31 | return &(accessCache(i_chip)); |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 32 | } |
| 33 | |
| 34 | //------------------------------------------------------------------------------ |
| 35 | |
Zane Shelley | fe27b65 | 2019-10-28 11:33:07 -0500 | [diff] [blame] | 36 | BitString& HardwareRegister::accessBitString(const Chip& i_chip) |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 37 | { |
Zane Shelley | 53efc35 | 2019-10-03 21:46:39 -0500 | [diff] [blame] | 38 | // Verify this register belongs on i_chip. |
Zane Shelley | 83da245 | 2019-10-25 15:45:34 -0500 | [diff] [blame] | 39 | verifyAccessorChip(i_chip); |
Zane Shelley | 53efc35 | 2019-10-03 21:46:39 -0500 | [diff] [blame] | 40 | |
Paul Greenwood | 6574f6e | 2019-09-17 09:43:22 -0500 | [diff] [blame] | 41 | // Calling read() will ensure that an entry exists in the cache and the |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 42 | // entry has at been synched with hardware at least once. Note that we |
| 43 | // cannot read hardware for write-only registers. In this case, an entry |
Zane Shelley | d0af358 | 2019-09-19 10:48:59 -0500 | [diff] [blame] | 44 | // will be created in the cache, if it does not exist, when the cache is |
Zane Shelley | 53efc35 | 2019-10-03 21:46:39 -0500 | [diff] [blame] | 45 | // accessed below. |
Zane Shelley | d0af358 | 2019-09-19 10:48:59 -0500 | [diff] [blame] | 46 | |
Zane Shelley | 7667b71 | 2020-05-11 20:45:40 -0500 | [diff] [blame^] | 47 | if (queryAttrFlag(REG_ATTR_ACCESS_READ)) |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 48 | { |
Zane Shelley | 83da245 | 2019-10-25 15:45:34 -0500 | [diff] [blame] | 49 | read(i_chip); |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 50 | } |
| 51 | |
Zane Shelley | 83da245 | 2019-10-25 15:45:34 -0500 | [diff] [blame] | 52 | return accessCache(i_chip); |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 53 | } |
| 54 | |
| 55 | //------------------------------------------------------------------------------ |
| 56 | |
Zane Shelley | 2f4aa91 | 2020-05-08 14:28:18 -0500 | [diff] [blame] | 57 | bool HardwareRegister::read(const Chip& i_chip, bool i_force) const |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 58 | { |
Zane Shelley | 2f4aa91 | 2020-05-08 14:28:18 -0500 | [diff] [blame] | 59 | bool accessFailure = false; |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 60 | |
Zane Shelley | 53efc35 | 2019-10-03 21:46:39 -0500 | [diff] [blame] | 61 | // Verify this register belongs on i_chip. |
Zane Shelley | 83da245 | 2019-10-25 15:45:34 -0500 | [diff] [blame] | 62 | verifyAccessorChip(i_chip); |
Zane Shelley | 53efc35 | 2019-10-03 21:46:39 -0500 | [diff] [blame] | 63 | |
Zane Shelley | 61565dc | 2019-09-18 21:57:10 -0500 | [diff] [blame] | 64 | // Read from hardware only if the read is forced or the entry for this |
| 65 | // instance does not exist in the cache. |
Zane Shelley | 83da245 | 2019-10-25 15:45:34 -0500 | [diff] [blame] | 66 | if (i_force || !queryCache(i_chip)) |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 67 | { |
Zane Shelley | 61565dc | 2019-09-18 21:57:10 -0500 | [diff] [blame] | 68 | // This register must be readable. |
Zane Shelley | 7667b71 | 2020-05-11 20:45:40 -0500 | [diff] [blame^] | 69 | HEI_ASSERT(queryAttrFlag(REG_ATTR_ACCESS_READ)); |
Zane Shelley | 61565dc | 2019-09-18 21:57:10 -0500 | [diff] [blame] | 70 | |
| 71 | // Get the buffer from the register cache. |
Zane Shelley | fe27b65 | 2019-10-28 11:33:07 -0500 | [diff] [blame] | 72 | BitString& bs = accessCache(i_chip); |
Zane Shelley | 61565dc | 2019-09-18 21:57:10 -0500 | [diff] [blame] | 73 | |
| 74 | // Get the byte size of the buffer. |
Zane Shelley | 83da245 | 2019-10-25 15:45:34 -0500 | [diff] [blame] | 75 | size_t sz_buffer = BitString::getMinBytes(bs.getBitLen()); |
Zane Shelley | 61565dc | 2019-09-18 21:57:10 -0500 | [diff] [blame] | 76 | |
| 77 | // Read this register from hardware. |
Zane Shelley | 2f4aa91 | 2020-05-08 14:28:18 -0500 | [diff] [blame] | 78 | accessFailure = registerRead(i_chip, bs.getBufAddr(), sz_buffer, |
| 79 | getRegisterType(), getAddress()); |
| 80 | if (accessFailure) |
Zane Shelley | 61565dc | 2019-09-18 21:57:10 -0500 | [diff] [blame] | 81 | { |
| 82 | // The read failed and we can't trust what was put in the register |
| 83 | // cache. So remove this instance's entry from the cache. |
Zane Shelley | 83da245 | 2019-10-25 15:45:34 -0500 | [diff] [blame] | 84 | flush(i_chip); |
Zane Shelley | 61565dc | 2019-09-18 21:57:10 -0500 | [diff] [blame] | 85 | } |
| 86 | else |
| 87 | { |
| 88 | // Sanity check. The returned size of the data written to the buffer |
| 89 | // should match the register size. |
Zane Shelley | 83da245 | 2019-10-25 15:45:34 -0500 | [diff] [blame] | 90 | HEI_ASSERT(getSize() == sz_buffer); |
Zane Shelley | 61565dc | 2019-09-18 21:57:10 -0500 | [diff] [blame] | 91 | } |
Zane Shelley | d0af358 | 2019-09-19 10:48:59 -0500 | [diff] [blame] | 92 | } |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 93 | |
Zane Shelley | 2f4aa91 | 2020-05-08 14:28:18 -0500 | [diff] [blame] | 94 | return accessFailure; |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 95 | } |
| 96 | |
| 97 | //------------------------------------------------------------------------------ |
| 98 | |
Ben Tyner | 7b3420b | 2020-05-11 10:52:07 -0500 | [diff] [blame] | 99 | #ifdef __HEI_ENABLE_HW_WRITE |
Zane Shelley | 61565dc | 2019-09-18 21:57:10 -0500 | [diff] [blame] | 100 | |
Zane Shelley | 2f4aa91 | 2020-05-08 14:28:18 -0500 | [diff] [blame] | 101 | bool HardwareRegister::write(const Chip& i_chip) const |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 102 | { |
Zane Shelley | 2f4aa91 | 2020-05-08 14:28:18 -0500 | [diff] [blame] | 103 | bool accessFailure = false; |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 104 | |
Zane Shelley | 53efc35 | 2019-10-03 21:46:39 -0500 | [diff] [blame] | 105 | // Verify this register belongs on i_chip. |
Zane Shelley | 83da245 | 2019-10-25 15:45:34 -0500 | [diff] [blame] | 106 | verifyAccessorChip(i_chip); |
Zane Shelley | 53efc35 | 2019-10-03 21:46:39 -0500 | [diff] [blame] | 107 | |
Zane Shelley | 61565dc | 2019-09-18 21:57:10 -0500 | [diff] [blame] | 108 | // This register must be writable. |
Zane Shelley | 7667b71 | 2020-05-11 20:45:40 -0500 | [diff] [blame^] | 109 | HEI_ASSERT(queryAttrFlag(REG_ATTR_ACCESS_WRITE)); |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 110 | |
Zane Shelley | 61565dc | 2019-09-18 21:57:10 -0500 | [diff] [blame] | 111 | // An entry for this register must exist in the cache. |
Zane Shelley | 83da245 | 2019-10-25 15:45:34 -0500 | [diff] [blame] | 112 | HEI_ASSERT(queryCache(i_chip)); |
Zane Shelley | 61565dc | 2019-09-18 21:57:10 -0500 | [diff] [blame] | 113 | |
| 114 | // Get the buffer from the register cache. |
Zane Shelley | fe27b65 | 2019-10-28 11:33:07 -0500 | [diff] [blame] | 115 | BitString& bs = accessCache(i_chip); |
Zane Shelley | 61565dc | 2019-09-18 21:57:10 -0500 | [diff] [blame] | 116 | |
| 117 | // Get the byte size of the buffer. |
Zane Shelley | 83da245 | 2019-10-25 15:45:34 -0500 | [diff] [blame] | 118 | size_t sz_buffer = BitString::getMinBytes(bs.getBitLen()); |
Zane Shelley | 61565dc | 2019-09-18 21:57:10 -0500 | [diff] [blame] | 119 | |
| 120 | // Write to this register to hardware. |
Zane Shelley | 2f4aa91 | 2020-05-08 14:28:18 -0500 | [diff] [blame] | 121 | accessFailure = registerWrite(i_chip, bs.getBufAddr(), sz_buffer, |
| 122 | getRegisterType(), getAddress()); |
Zane Shelley | 61565dc | 2019-09-18 21:57:10 -0500 | [diff] [blame] | 123 | |
Zane Shelley | 2f4aa91 | 2020-05-08 14:28:18 -0500 | [diff] [blame] | 124 | if (accessFailure) |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 125 | { |
Zane Shelley | 61565dc | 2019-09-18 21:57:10 -0500 | [diff] [blame] | 126 | // Sanity check. The returned size of the data written to the buffer |
| 127 | // should match the register size. |
Zane Shelley | 83da245 | 2019-10-25 15:45:34 -0500 | [diff] [blame] | 128 | HEI_ASSERT(getSize() == sz_buffer); |
Zane Shelley | 61565dc | 2019-09-18 21:57:10 -0500 | [diff] [blame] | 129 | } |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 130 | |
Zane Shelley | 2f4aa91 | 2020-05-08 14:28:18 -0500 | [diff] [blame] | 131 | return accessFailure; |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 132 | } |
| 133 | |
Ben Tyner | 7b3420b | 2020-05-11 10:52:07 -0500 | [diff] [blame] | 134 | #endif // __HEI_ENABLE_HW_WRITE |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 135 | |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 136 | //------------------------------------------------------------------------------ |
| 137 | |
Zane Shelley | c477199 | 2019-10-28 22:01:49 -0500 | [diff] [blame] | 138 | HardwareRegister::Cache HardwareRegister::cv_cache{}; |
Zane Shelley | d0af358 | 2019-09-19 10:48:59 -0500 | [diff] [blame] | 139 | |
| 140 | //------------------------------------------------------------------------------ |
| 141 | |
Zane Shelley | fe27b65 | 2019-10-28 11:33:07 -0500 | [diff] [blame] | 142 | bool HardwareRegister::Cache::query(const Chip& i_chip, |
| 143 | const HardwareRegister* i_hwReg) const |
Zane Shelley | d0af358 | 2019-09-19 10:48:59 -0500 | [diff] [blame] | 144 | { |
| 145 | // Does i_chip exist in the cache? |
Zane Shelley | 83da245 | 2019-10-25 15:45:34 -0500 | [diff] [blame] | 146 | auto chipPairItr = iv_cache.find(i_chip); |
| 147 | if (iv_cache.end() != chipPairItr) |
Zane Shelley | d0af358 | 2019-09-19 10:48:59 -0500 | [diff] [blame] | 148 | { |
Zane Shelley | fe27b65 | 2019-10-28 11:33:07 -0500 | [diff] [blame] | 149 | auto& hwRegMap = chipPairItr->second; // for ease of use |
Zane Shelley | d0af358 | 2019-09-19 10:48:59 -0500 | [diff] [blame] | 150 | |
| 151 | // Does i_hwReg exist in the cache? |
Zane Shelley | 83da245 | 2019-10-25 15:45:34 -0500 | [diff] [blame] | 152 | auto hwRegPairItr = hwRegMap.find(i_hwReg); |
| 153 | if (hwRegMap.end() != hwRegPairItr) |
Zane Shelley | d0af358 | 2019-09-19 10:48:59 -0500 | [diff] [blame] | 154 | { |
| 155 | return true; |
| 156 | } |
| 157 | } |
| 158 | |
| 159 | return false; |
| 160 | } |
| 161 | |
| 162 | //------------------------------------------------------------------------------ |
| 163 | |
Zane Shelley | fe27b65 | 2019-10-28 11:33:07 -0500 | [diff] [blame] | 164 | BitString& HardwareRegister::Cache::access(const Chip& i_chip, |
Zane Shelley | c477199 | 2019-10-28 22:01:49 -0500 | [diff] [blame] | 165 | const HardwareRegister* i_hwReg) |
Zane Shelley | d0af358 | 2019-09-19 10:48:59 -0500 | [diff] [blame] | 166 | { |
| 167 | // If the entry does not exist, create a new entry. |
Zane Shelley | 83da245 | 2019-10-25 15:45:34 -0500 | [diff] [blame] | 168 | if (!query(i_chip, i_hwReg)) |
Zane Shelley | d0af358 | 2019-09-19 10:48:59 -0500 | [diff] [blame] | 169 | { |
Zane Shelley | c477199 | 2019-10-28 22:01:49 -0500 | [diff] [blame] | 170 | BitString* bs = new BitStringBuffer{i_hwReg->getSize() * 8}; |
Zane Shelley | 7c8faa1 | 2019-10-28 22:26:28 -0500 | [diff] [blame] | 171 | |
Zane Shelley | d0af358 | 2019-09-19 10:48:59 -0500 | [diff] [blame] | 172 | iv_cache[i_chip][i_hwReg] = bs; |
| 173 | } |
| 174 | |
| 175 | // Return a reference to the target entry. |
| 176 | return *(iv_cache[i_chip][i_hwReg]); |
| 177 | } |
| 178 | |
| 179 | //------------------------------------------------------------------------------ |
| 180 | |
| 181 | void HardwareRegister::Cache::flush() |
| 182 | { |
| 183 | // Delete all of the BitStrings. |
Zane Shelley | fe27b65 | 2019-10-28 11:33:07 -0500 | [diff] [blame] | 184 | for (auto& chipPair : iv_cache) |
Zane Shelley | d0af358 | 2019-09-19 10:48:59 -0500 | [diff] [blame] | 185 | { |
Zane Shelley | fe27b65 | 2019-10-28 11:33:07 -0500 | [diff] [blame] | 186 | for (auto& hwRegPair : chipPair.second) |
Zane Shelley | d0af358 | 2019-09-19 10:48:59 -0500 | [diff] [blame] | 187 | { |
| 188 | delete hwRegPair.second; |
| 189 | } |
| 190 | } |
| 191 | |
| 192 | // !!! Do not delete the HardwareRegisters !!! |
| 193 | // Those are deleted when the main uninitialize() API is called. |
| 194 | |
| 195 | // Flush the rest of the cache. |
| 196 | iv_cache.clear(); |
| 197 | } |
| 198 | |
| 199 | //------------------------------------------------------------------------------ |
| 200 | |
Zane Shelley | fe27b65 | 2019-10-28 11:33:07 -0500 | [diff] [blame] | 201 | void HardwareRegister::Cache::flush(const Chip& i_chip, |
| 202 | const HardwareRegister* i_hwReg) |
Zane Shelley | d0af358 | 2019-09-19 10:48:59 -0500 | [diff] [blame] | 203 | { |
| 204 | // Does i_chip exist in the cache? |
Zane Shelley | 83da245 | 2019-10-25 15:45:34 -0500 | [diff] [blame] | 205 | auto chipPairItr = iv_cache.find(i_chip); |
| 206 | if (iv_cache.end() != chipPairItr) |
Zane Shelley | d0af358 | 2019-09-19 10:48:59 -0500 | [diff] [blame] | 207 | { |
Zane Shelley | fe27b65 | 2019-10-28 11:33:07 -0500 | [diff] [blame] | 208 | auto& hwRegMap = chipPairItr->second; // for ease of use |
Zane Shelley | d0af358 | 2019-09-19 10:48:59 -0500 | [diff] [blame] | 209 | |
| 210 | // Does i_hwReg exist in the cache? |
Zane Shelley | 83da245 | 2019-10-25 15:45:34 -0500 | [diff] [blame] | 211 | auto hwRegPairItr = hwRegMap.find(i_hwReg); |
| 212 | if (hwRegMap.end() != hwRegPairItr) |
Zane Shelley | d0af358 | 2019-09-19 10:48:59 -0500 | [diff] [blame] | 213 | { |
| 214 | delete hwRegPairItr->second; // delete the BitString |
| 215 | hwRegMap.erase(i_hwReg); // remove the entry for this register |
| 216 | } |
| 217 | |
| 218 | // If i_hwReg was the only entry for i_chip, we can remove i_chip from |
| 219 | // the cache. |
Zane Shelley | 83da245 | 2019-10-25 15:45:34 -0500 | [diff] [blame] | 220 | if (hwRegMap.empty()) |
Zane Shelley | d0af358 | 2019-09-19 10:48:59 -0500 | [diff] [blame] | 221 | { |
| 222 | iv_cache.erase(i_chip); |
| 223 | } |
| 224 | } |
| 225 | } |
| 226 | |
| 227 | //------------------------------------------------------------------------------ |
| 228 | |
Zane Shelley | 871adec | 2019-07-30 11:01:39 -0500 | [diff] [blame] | 229 | } // end namespace libhei |