Zane Shelley | 52cb1a9 | 2019-08-21 14:38:31 -0500 | [diff] [blame] | 1 | #include <hei_includes.hpp> |
Zane Shelley | 61565dc | 2019-09-18 21:57:10 -0500 | [diff] [blame] | 2 | #include <hei_user_interface.hpp> |
Zane Shelley | 52cb1a9 | 2019-08-21 14:38:31 -0500 | [diff] [blame] | 3 | #include <register/hei_hardware_register.hpp> |
| 4 | #include <util/hei_bit_string.hpp> |
| 5 | |
Zane Shelley | 871adec | 2019-07-30 11:01:39 -0500 | [diff] [blame] | 6 | namespace libhei |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 7 | { |
| 8 | |
Zane Shelley | 8deb090 | 2019-10-14 15:52:27 -0500 | [diff] [blame] | 9 | //------------------------------------------------------------------------------ |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 10 | |
Zane Shelley | 8deb090 | 2019-10-14 15:52:27 -0500 | [diff] [blame] | 11 | HardwareRegister::~HardwareRegister() {} |
| 12 | |
| 13 | //------------------------------------------------------------------------------ |
| 14 | |
Zane Shelley | fe27b65 | 2019-10-28 11:33:07 -0500 | [diff] [blame] | 15 | const BitString* HardwareRegister::getBitString(const Chip& i_chip) const |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 16 | { |
Paul Greenwood | 6574f6e | 2019-09-17 09:43:22 -0500 | [diff] [blame] | 17 | // Calling read() will ensure that an entry exists in the cache and the |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 18 | // entry has at been synched with hardware at least once. Note that we |
| 19 | // cannot read hardware for write-only registers. In this case, an entry |
Zane Shelley | d0af358 | 2019-09-19 10:48:59 -0500 | [diff] [blame] | 20 | // will be created in the cache, if it does not exist, when the cache is |
Zane Shelley | 53efc35 | 2019-10-03 21:46:39 -0500 | [diff] [blame] | 21 | // accessed below. |
Zane Shelley | d0af358 | 2019-09-19 10:48:59 -0500 | [diff] [blame] | 22 | |
Zane Shelley | 7667b71 | 2020-05-11 20:45:40 -0500 | [diff] [blame] | 23 | if (queryAttrFlag(REG_ATTR_ACCESS_READ)) |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 24 | { |
Zane Shelley | 83da245 | 2019-10-25 15:45:34 -0500 | [diff] [blame] | 25 | read(i_chip); |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 26 | } |
Zane Shelley | d0af358 | 2019-09-19 10:48:59 -0500 | [diff] [blame] | 27 | |
Zane Shelley | 83da245 | 2019-10-25 15:45:34 -0500 | [diff] [blame] | 28 | return &(accessCache(i_chip)); |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 29 | } |
| 30 | |
| 31 | //------------------------------------------------------------------------------ |
| 32 | |
Zane Shelley | fe27b65 | 2019-10-28 11:33:07 -0500 | [diff] [blame] | 33 | BitString& HardwareRegister::accessBitString(const Chip& i_chip) |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 34 | { |
Paul Greenwood | 6574f6e | 2019-09-17 09:43:22 -0500 | [diff] [blame] | 35 | // Calling read() will ensure that an entry exists in the cache and the |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 36 | // entry has at been synched with hardware at least once. Note that we |
| 37 | // cannot read hardware for write-only registers. In this case, an entry |
Zane Shelley | d0af358 | 2019-09-19 10:48:59 -0500 | [diff] [blame] | 38 | // will be created in the cache, if it does not exist, when the cache is |
Zane Shelley | 53efc35 | 2019-10-03 21:46:39 -0500 | [diff] [blame] | 39 | // accessed below. |
Zane Shelley | d0af358 | 2019-09-19 10:48:59 -0500 | [diff] [blame] | 40 | |
Zane Shelley | 7667b71 | 2020-05-11 20:45:40 -0500 | [diff] [blame] | 41 | if (queryAttrFlag(REG_ATTR_ACCESS_READ)) |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 42 | { |
Zane Shelley | 83da245 | 2019-10-25 15:45:34 -0500 | [diff] [blame] | 43 | read(i_chip); |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 44 | } |
| 45 | |
Zane Shelley | 83da245 | 2019-10-25 15:45:34 -0500 | [diff] [blame] | 46 | return accessCache(i_chip); |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 47 | } |
| 48 | |
| 49 | //------------------------------------------------------------------------------ |
| 50 | |
Zane Shelley | 2f4aa91 | 2020-05-08 14:28:18 -0500 | [diff] [blame] | 51 | bool HardwareRegister::read(const Chip& i_chip, bool i_force) const |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 52 | { |
Zane Shelley | 2f4aa91 | 2020-05-08 14:28:18 -0500 | [diff] [blame] | 53 | bool accessFailure = false; |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 54 | |
Zane Shelley | 61565dc | 2019-09-18 21:57:10 -0500 | [diff] [blame] | 55 | // Read from hardware only if the read is forced or the entry for this |
| 56 | // instance does not exist in the cache. |
Zane Shelley | 83da245 | 2019-10-25 15:45:34 -0500 | [diff] [blame] | 57 | if (i_force || !queryCache(i_chip)) |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 58 | { |
Zane Shelley | 61565dc | 2019-09-18 21:57:10 -0500 | [diff] [blame] | 59 | // This register must be readable. |
Zane Shelley | 7667b71 | 2020-05-11 20:45:40 -0500 | [diff] [blame] | 60 | HEI_ASSERT(queryAttrFlag(REG_ATTR_ACCESS_READ)); |
Zane Shelley | 61565dc | 2019-09-18 21:57:10 -0500 | [diff] [blame] | 61 | |
| 62 | // Get the buffer from the register cache. |
Zane Shelley | fe27b65 | 2019-10-28 11:33:07 -0500 | [diff] [blame] | 63 | BitString& bs = accessCache(i_chip); |
Zane Shelley | 61565dc | 2019-09-18 21:57:10 -0500 | [diff] [blame] | 64 | |
| 65 | // Get the byte size of the buffer. |
Zane Shelley | 83da245 | 2019-10-25 15:45:34 -0500 | [diff] [blame] | 66 | size_t sz_buffer = BitString::getMinBytes(bs.getBitLen()); |
Zane Shelley | 61565dc | 2019-09-18 21:57:10 -0500 | [diff] [blame] | 67 | |
| 68 | // Read this register from hardware. |
Zane Shelley | 2f4aa91 | 2020-05-08 14:28:18 -0500 | [diff] [blame] | 69 | accessFailure = registerRead(i_chip, bs.getBufAddr(), sz_buffer, |
Zane Shelley | 5ec8810 | 2020-05-11 21:08:25 -0500 | [diff] [blame^] | 70 | getType(), getAddress()); |
Zane Shelley | 2f4aa91 | 2020-05-08 14:28:18 -0500 | [diff] [blame] | 71 | if (accessFailure) |
Zane Shelley | 61565dc | 2019-09-18 21:57:10 -0500 | [diff] [blame] | 72 | { |
| 73 | // The read failed and we can't trust what was put in the register |
| 74 | // cache. So remove this instance's entry from the cache. |
Zane Shelley | 83da245 | 2019-10-25 15:45:34 -0500 | [diff] [blame] | 75 | flush(i_chip); |
Zane Shelley | 61565dc | 2019-09-18 21:57:10 -0500 | [diff] [blame] | 76 | } |
| 77 | else |
| 78 | { |
| 79 | // Sanity check. The returned size of the data written to the buffer |
| 80 | // should match the register size. |
Zane Shelley | 83da245 | 2019-10-25 15:45:34 -0500 | [diff] [blame] | 81 | HEI_ASSERT(getSize() == sz_buffer); |
Zane Shelley | 61565dc | 2019-09-18 21:57:10 -0500 | [diff] [blame] | 82 | } |
Zane Shelley | d0af358 | 2019-09-19 10:48:59 -0500 | [diff] [blame] | 83 | } |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 84 | |
Zane Shelley | 2f4aa91 | 2020-05-08 14:28:18 -0500 | [diff] [blame] | 85 | return accessFailure; |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 86 | } |
| 87 | |
| 88 | //------------------------------------------------------------------------------ |
| 89 | |
Ben Tyner | 7b3420b | 2020-05-11 10:52:07 -0500 | [diff] [blame] | 90 | #ifdef __HEI_ENABLE_HW_WRITE |
Zane Shelley | 61565dc | 2019-09-18 21:57:10 -0500 | [diff] [blame] | 91 | |
Zane Shelley | 2f4aa91 | 2020-05-08 14:28:18 -0500 | [diff] [blame] | 92 | bool HardwareRegister::write(const Chip& i_chip) const |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 93 | { |
Zane Shelley | 2f4aa91 | 2020-05-08 14:28:18 -0500 | [diff] [blame] | 94 | bool accessFailure = false; |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 95 | |
Zane Shelley | 61565dc | 2019-09-18 21:57:10 -0500 | [diff] [blame] | 96 | // This register must be writable. |
Zane Shelley | 7667b71 | 2020-05-11 20:45:40 -0500 | [diff] [blame] | 97 | HEI_ASSERT(queryAttrFlag(REG_ATTR_ACCESS_WRITE)); |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 98 | |
Zane Shelley | 61565dc | 2019-09-18 21:57:10 -0500 | [diff] [blame] | 99 | // An entry for this register must exist in the cache. |
Zane Shelley | 83da245 | 2019-10-25 15:45:34 -0500 | [diff] [blame] | 100 | HEI_ASSERT(queryCache(i_chip)); |
Zane Shelley | 61565dc | 2019-09-18 21:57:10 -0500 | [diff] [blame] | 101 | |
| 102 | // Get the buffer from the register cache. |
Zane Shelley | fe27b65 | 2019-10-28 11:33:07 -0500 | [diff] [blame] | 103 | BitString& bs = accessCache(i_chip); |
Zane Shelley | 61565dc | 2019-09-18 21:57:10 -0500 | [diff] [blame] | 104 | |
| 105 | // Get the byte size of the buffer. |
Zane Shelley | 83da245 | 2019-10-25 15:45:34 -0500 | [diff] [blame] | 106 | size_t sz_buffer = BitString::getMinBytes(bs.getBitLen()); |
Zane Shelley | 61565dc | 2019-09-18 21:57:10 -0500 | [diff] [blame] | 107 | |
| 108 | // Write to this register to hardware. |
Zane Shelley | 5ec8810 | 2020-05-11 21:08:25 -0500 | [diff] [blame^] | 109 | accessFailure = registerWrite(i_chip, bs.getBufAddr(), sz_buffer, getType(), |
| 110 | getAddress()); |
Zane Shelley | 61565dc | 2019-09-18 21:57:10 -0500 | [diff] [blame] | 111 | |
Zane Shelley | 2f4aa91 | 2020-05-08 14:28:18 -0500 | [diff] [blame] | 112 | if (accessFailure) |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 113 | { |
Zane Shelley | 61565dc | 2019-09-18 21:57:10 -0500 | [diff] [blame] | 114 | // Sanity check. The returned size of the data written to the buffer |
| 115 | // should match the register size. |
Zane Shelley | 83da245 | 2019-10-25 15:45:34 -0500 | [diff] [blame] | 116 | HEI_ASSERT(getSize() == sz_buffer); |
Zane Shelley | 61565dc | 2019-09-18 21:57:10 -0500 | [diff] [blame] | 117 | } |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 118 | |
Zane Shelley | 2f4aa91 | 2020-05-08 14:28:18 -0500 | [diff] [blame] | 119 | return accessFailure; |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 120 | } |
| 121 | |
Ben Tyner | 7b3420b | 2020-05-11 10:52:07 -0500 | [diff] [blame] | 122 | #endif // __HEI_ENABLE_HW_WRITE |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 123 | |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 124 | //------------------------------------------------------------------------------ |
| 125 | |
Zane Shelley | c477199 | 2019-10-28 22:01:49 -0500 | [diff] [blame] | 126 | HardwareRegister::Cache HardwareRegister::cv_cache{}; |
Zane Shelley | d0af358 | 2019-09-19 10:48:59 -0500 | [diff] [blame] | 127 | |
| 128 | //------------------------------------------------------------------------------ |
| 129 | |
Zane Shelley | fe27b65 | 2019-10-28 11:33:07 -0500 | [diff] [blame] | 130 | bool HardwareRegister::Cache::query(const Chip& i_chip, |
| 131 | const HardwareRegister* i_hwReg) const |
Zane Shelley | d0af358 | 2019-09-19 10:48:59 -0500 | [diff] [blame] | 132 | { |
| 133 | // Does i_chip exist in the cache? |
Zane Shelley | 83da245 | 2019-10-25 15:45:34 -0500 | [diff] [blame] | 134 | auto chipPairItr = iv_cache.find(i_chip); |
| 135 | if (iv_cache.end() != chipPairItr) |
Zane Shelley | d0af358 | 2019-09-19 10:48:59 -0500 | [diff] [blame] | 136 | { |
Zane Shelley | fe27b65 | 2019-10-28 11:33:07 -0500 | [diff] [blame] | 137 | auto& hwRegMap = chipPairItr->second; // for ease of use |
Zane Shelley | d0af358 | 2019-09-19 10:48:59 -0500 | [diff] [blame] | 138 | |
| 139 | // Does i_hwReg exist in the cache? |
Zane Shelley | 83da245 | 2019-10-25 15:45:34 -0500 | [diff] [blame] | 140 | auto hwRegPairItr = hwRegMap.find(i_hwReg); |
| 141 | if (hwRegMap.end() != hwRegPairItr) |
Zane Shelley | d0af358 | 2019-09-19 10:48:59 -0500 | [diff] [blame] | 142 | { |
| 143 | return true; |
| 144 | } |
| 145 | } |
| 146 | |
| 147 | return false; |
| 148 | } |
| 149 | |
| 150 | //------------------------------------------------------------------------------ |
| 151 | |
Zane Shelley | fe27b65 | 2019-10-28 11:33:07 -0500 | [diff] [blame] | 152 | BitString& HardwareRegister::Cache::access(const Chip& i_chip, |
Zane Shelley | c477199 | 2019-10-28 22:01:49 -0500 | [diff] [blame] | 153 | const HardwareRegister* i_hwReg) |
Zane Shelley | d0af358 | 2019-09-19 10:48:59 -0500 | [diff] [blame] | 154 | { |
| 155 | // If the entry does not exist, create a new entry. |
Zane Shelley | 83da245 | 2019-10-25 15:45:34 -0500 | [diff] [blame] | 156 | if (!query(i_chip, i_hwReg)) |
Zane Shelley | d0af358 | 2019-09-19 10:48:59 -0500 | [diff] [blame] | 157 | { |
Zane Shelley | c477199 | 2019-10-28 22:01:49 -0500 | [diff] [blame] | 158 | BitString* bs = new BitStringBuffer{i_hwReg->getSize() * 8}; |
Zane Shelley | 7c8faa1 | 2019-10-28 22:26:28 -0500 | [diff] [blame] | 159 | |
Zane Shelley | d0af358 | 2019-09-19 10:48:59 -0500 | [diff] [blame] | 160 | iv_cache[i_chip][i_hwReg] = bs; |
| 161 | } |
| 162 | |
| 163 | // Return a reference to the target entry. |
| 164 | return *(iv_cache[i_chip][i_hwReg]); |
| 165 | } |
| 166 | |
| 167 | //------------------------------------------------------------------------------ |
| 168 | |
| 169 | void HardwareRegister::Cache::flush() |
| 170 | { |
| 171 | // Delete all of the BitStrings. |
Zane Shelley | fe27b65 | 2019-10-28 11:33:07 -0500 | [diff] [blame] | 172 | for (auto& chipPair : iv_cache) |
Zane Shelley | d0af358 | 2019-09-19 10:48:59 -0500 | [diff] [blame] | 173 | { |
Zane Shelley | fe27b65 | 2019-10-28 11:33:07 -0500 | [diff] [blame] | 174 | for (auto& hwRegPair : chipPair.second) |
Zane Shelley | d0af358 | 2019-09-19 10:48:59 -0500 | [diff] [blame] | 175 | { |
| 176 | delete hwRegPair.second; |
| 177 | } |
| 178 | } |
| 179 | |
| 180 | // !!! Do not delete the HardwareRegisters !!! |
| 181 | // Those are deleted when the main uninitialize() API is called. |
| 182 | |
| 183 | // Flush the rest of the cache. |
| 184 | iv_cache.clear(); |
| 185 | } |
| 186 | |
| 187 | //------------------------------------------------------------------------------ |
| 188 | |
Zane Shelley | fe27b65 | 2019-10-28 11:33:07 -0500 | [diff] [blame] | 189 | void HardwareRegister::Cache::flush(const Chip& i_chip, |
| 190 | const HardwareRegister* i_hwReg) |
Zane Shelley | d0af358 | 2019-09-19 10:48:59 -0500 | [diff] [blame] | 191 | { |
| 192 | // Does i_chip exist in the cache? |
Zane Shelley | 83da245 | 2019-10-25 15:45:34 -0500 | [diff] [blame] | 193 | auto chipPairItr = iv_cache.find(i_chip); |
| 194 | if (iv_cache.end() != chipPairItr) |
Zane Shelley | d0af358 | 2019-09-19 10:48:59 -0500 | [diff] [blame] | 195 | { |
Zane Shelley | fe27b65 | 2019-10-28 11:33:07 -0500 | [diff] [blame] | 196 | auto& hwRegMap = chipPairItr->second; // for ease of use |
Zane Shelley | d0af358 | 2019-09-19 10:48:59 -0500 | [diff] [blame] | 197 | |
| 198 | // Does i_hwReg exist in the cache? |
Zane Shelley | 83da245 | 2019-10-25 15:45:34 -0500 | [diff] [blame] | 199 | auto hwRegPairItr = hwRegMap.find(i_hwReg); |
| 200 | if (hwRegMap.end() != hwRegPairItr) |
Zane Shelley | d0af358 | 2019-09-19 10:48:59 -0500 | [diff] [blame] | 201 | { |
| 202 | delete hwRegPairItr->second; // delete the BitString |
| 203 | hwRegMap.erase(i_hwReg); // remove the entry for this register |
| 204 | } |
| 205 | |
| 206 | // If i_hwReg was the only entry for i_chip, we can remove i_chip from |
| 207 | // the cache. |
Zane Shelley | 83da245 | 2019-10-25 15:45:34 -0500 | [diff] [blame] | 208 | if (hwRegMap.empty()) |
Zane Shelley | d0af358 | 2019-09-19 10:48:59 -0500 | [diff] [blame] | 209 | { |
| 210 | iv_cache.erase(i_chip); |
| 211 | } |
| 212 | } |
| 213 | } |
| 214 | |
| 215 | //------------------------------------------------------------------------------ |
| 216 | |
Zane Shelley | 871adec | 2019-07-30 11:01:39 -0500 | [diff] [blame] | 217 | } // end namespace libhei |