Zane Shelley | 61565dc | 2019-09-18 21:57:10 -0500 | [diff] [blame] | 1 | #include <hei_user_interface.hpp> |
Zane Shelley | 52cb1a9 | 2019-08-21 14:38:31 -0500 | [diff] [blame] | 2 | #include <register/hei_hardware_register.hpp> |
Zane Shelley | 995be6c | 2021-02-24 15:48:55 -0600 | [diff] [blame] | 3 | #include <util/hei_bit_string.hpp> |
Zane Shelley | d507351 | 2021-01-14 12:51:18 -0600 | [diff] [blame] | 4 | #include <util/hei_includes.hpp> |
Zane Shelley | 52cb1a9 | 2019-08-21 14:38:31 -0500 | [diff] [blame] | 5 | |
Zane Shelley | 871adec | 2019-07-30 11:01:39 -0500 | [diff] [blame] | 6 | namespace libhei |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 7 | { |
| 8 | |
Zane Shelley | 8deb090 | 2019-10-14 15:52:27 -0500 | [diff] [blame] | 9 | //------------------------------------------------------------------------------ |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 10 | |
Zane Shelley | 8deb090 | 2019-10-14 15:52:27 -0500 | [diff] [blame] | 11 | HardwareRegister::~HardwareRegister() {} |
| 12 | |
| 13 | //------------------------------------------------------------------------------ |
| 14 | |
Zane Shelley | fe27b65 | 2019-10-28 11:33:07 -0500 | [diff] [blame] | 15 | const BitString* HardwareRegister::getBitString(const Chip& i_chip) const |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 16 | { |
Paul Greenwood | 6574f6e | 2019-09-17 09:43:22 -0500 | [diff] [blame] | 17 | // Calling read() will ensure that an entry exists in the cache and the |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 18 | // entry has at been synched with hardware at least once. Note that we |
| 19 | // cannot read hardware for write-only registers. In this case, an entry |
Zane Shelley | d0af358 | 2019-09-19 10:48:59 -0500 | [diff] [blame] | 20 | // will be created in the cache, if it does not exist, when the cache is |
Zane Shelley | 53efc35 | 2019-10-03 21:46:39 -0500 | [diff] [blame] | 21 | // accessed below. |
Zane Shelley | d0af358 | 2019-09-19 10:48:59 -0500 | [diff] [blame] | 22 | |
Zane Shelley | 7667b71 | 2020-05-11 20:45:40 -0500 | [diff] [blame] | 23 | if (queryAttrFlag(REG_ATTR_ACCESS_READ)) |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 24 | { |
Zane Shelley | 83da245 | 2019-10-25 15:45:34 -0500 | [diff] [blame] | 25 | read(i_chip); |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 26 | } |
Zane Shelley | d0af358 | 2019-09-19 10:48:59 -0500 | [diff] [blame] | 27 | |
Zane Shelley | 83da245 | 2019-10-25 15:45:34 -0500 | [diff] [blame] | 28 | return &(accessCache(i_chip)); |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 29 | } |
| 30 | |
| 31 | //------------------------------------------------------------------------------ |
| 32 | |
Zane Shelley | fe27b65 | 2019-10-28 11:33:07 -0500 | [diff] [blame] | 33 | BitString& HardwareRegister::accessBitString(const Chip& i_chip) |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 34 | { |
Paul Greenwood | 6574f6e | 2019-09-17 09:43:22 -0500 | [diff] [blame] | 35 | // Calling read() will ensure that an entry exists in the cache and the |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 36 | // entry has at been synched with hardware at least once. Note that we |
| 37 | // cannot read hardware for write-only registers. In this case, an entry |
Zane Shelley | d0af358 | 2019-09-19 10:48:59 -0500 | [diff] [blame] | 38 | // will be created in the cache, if it does not exist, when the cache is |
Zane Shelley | 53efc35 | 2019-10-03 21:46:39 -0500 | [diff] [blame] | 39 | // accessed below. |
Zane Shelley | d0af358 | 2019-09-19 10:48:59 -0500 | [diff] [blame] | 40 | |
Zane Shelley | 7667b71 | 2020-05-11 20:45:40 -0500 | [diff] [blame] | 41 | if (queryAttrFlag(REG_ATTR_ACCESS_READ)) |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 42 | { |
Zane Shelley | 83da245 | 2019-10-25 15:45:34 -0500 | [diff] [blame] | 43 | read(i_chip); |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 44 | } |
| 45 | |
Zane Shelley | 83da245 | 2019-10-25 15:45:34 -0500 | [diff] [blame] | 46 | return accessCache(i_chip); |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 47 | } |
| 48 | |
| 49 | //------------------------------------------------------------------------------ |
| 50 | |
Zane Shelley | 2f4aa91 | 2020-05-08 14:28:18 -0500 | [diff] [blame] | 51 | bool HardwareRegister::read(const Chip& i_chip, bool i_force) const |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 52 | { |
Zane Shelley | 2f4aa91 | 2020-05-08 14:28:18 -0500 | [diff] [blame] | 53 | bool accessFailure = false; |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 54 | |
Zane Shelley | 2d4981a | 2020-06-04 14:32:45 -0500 | [diff] [blame] | 55 | // This register must be readable. |
| 56 | HEI_ASSERT(queryAttrFlag(REG_ATTR_ACCESS_READ)); |
| 57 | |
Zane Shelley | 61565dc | 2019-09-18 21:57:10 -0500 | [diff] [blame] | 58 | // Read from hardware only if the read is forced or the entry for this |
| 59 | // instance does not exist in the cache. |
Zane Shelley | 83da245 | 2019-10-25 15:45:34 -0500 | [diff] [blame] | 60 | if (i_force || !queryCache(i_chip)) |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 61 | { |
Zane Shelley | 61565dc | 2019-09-18 21:57:10 -0500 | [diff] [blame] | 62 | // Read this register from hardware. |
Zane Shelley | 2d4981a | 2020-06-04 14:32:45 -0500 | [diff] [blame] | 63 | uint64_t val = 0; |
| 64 | accessFailure = registerRead(i_chip, getType(), getAddress(), val); |
| 65 | if (!accessFailure) |
Zane Shelley | 61565dc | 2019-09-18 21:57:10 -0500 | [diff] [blame] | 66 | { |
Zane Shelley | 2d4981a | 2020-06-04 14:32:45 -0500 | [diff] [blame] | 67 | // Get the buffer from the register cache. |
| 68 | BitString& bs = accessCache(i_chip); |
| 69 | |
| 70 | // Set this value in the bit string buffer. |
| 71 | bs.setFieldRight(0, bs.getBitLen(), val); |
Zane Shelley | 61565dc | 2019-09-18 21:57:10 -0500 | [diff] [blame] | 72 | } |
Zane Shelley | d0af358 | 2019-09-19 10:48:59 -0500 | [diff] [blame] | 73 | } |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 74 | |
Zane Shelley | 2f4aa91 | 2020-05-08 14:28:18 -0500 | [diff] [blame] | 75 | return accessFailure; |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 76 | } |
| 77 | |
| 78 | //------------------------------------------------------------------------------ |
| 79 | |
Ben Tyner | 7b3420b | 2020-05-11 10:52:07 -0500 | [diff] [blame] | 80 | #ifdef __HEI_ENABLE_HW_WRITE |
Zane Shelley | 61565dc | 2019-09-18 21:57:10 -0500 | [diff] [blame] | 81 | |
Zane Shelley | 2f4aa91 | 2020-05-08 14:28:18 -0500 | [diff] [blame] | 82 | bool HardwareRegister::write(const Chip& i_chip) const |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 83 | { |
Zane Shelley | 61565dc | 2019-09-18 21:57:10 -0500 | [diff] [blame] | 84 | // This register must be writable. |
Zane Shelley | 7667b71 | 2020-05-11 20:45:40 -0500 | [diff] [blame] | 85 | HEI_ASSERT(queryAttrFlag(REG_ATTR_ACCESS_WRITE)); |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 86 | |
Zane Shelley | 61565dc | 2019-09-18 21:57:10 -0500 | [diff] [blame] | 87 | // An entry for this register must exist in the cache. |
Zane Shelley | 83da245 | 2019-10-25 15:45:34 -0500 | [diff] [blame] | 88 | HEI_ASSERT(queryCache(i_chip)); |
Zane Shelley | 61565dc | 2019-09-18 21:57:10 -0500 | [diff] [blame] | 89 | |
| 90 | // Get the buffer from the register cache. |
Zane Shelley | fe27b65 | 2019-10-28 11:33:07 -0500 | [diff] [blame] | 91 | BitString& bs = accessCache(i_chip); |
Zane Shelley | 61565dc | 2019-09-18 21:57:10 -0500 | [diff] [blame] | 92 | |
Zane Shelley | 2d4981a | 2020-06-04 14:32:45 -0500 | [diff] [blame] | 93 | // Set this value from the bit string buffer. |
| 94 | uint64_t val = bs.getFieldRight(0, bs.getBitLen()); |
Zane Shelley | 61565dc | 2019-09-18 21:57:10 -0500 | [diff] [blame] | 95 | |
| 96 | // Write to this register to hardware. |
Zane Shelley | 2d4981a | 2020-06-04 14:32:45 -0500 | [diff] [blame] | 97 | return registerWrite(i_chip, getType(), getAddress(), val); |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 98 | } |
| 99 | |
Ben Tyner | 7b3420b | 2020-05-11 10:52:07 -0500 | [diff] [blame] | 100 | #endif // __HEI_ENABLE_HW_WRITE |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 101 | |
Zane Shelley | fd3f9cc | 2019-07-29 15:02:24 -0500 | [diff] [blame] | 102 | //------------------------------------------------------------------------------ |
| 103 | |
Zane Shelley | c477199 | 2019-10-28 22:01:49 -0500 | [diff] [blame] | 104 | HardwareRegister::Cache HardwareRegister::cv_cache{}; |
Zane Shelley | d0af358 | 2019-09-19 10:48:59 -0500 | [diff] [blame] | 105 | |
| 106 | //------------------------------------------------------------------------------ |
| 107 | |
Zane Shelley | fe27b65 | 2019-10-28 11:33:07 -0500 | [diff] [blame] | 108 | bool HardwareRegister::Cache::query(const Chip& i_chip, |
| 109 | const HardwareRegister* i_hwReg) const |
Zane Shelley | d0af358 | 2019-09-19 10:48:59 -0500 | [diff] [blame] | 110 | { |
| 111 | // Does i_chip exist in the cache? |
Zane Shelley | 83da245 | 2019-10-25 15:45:34 -0500 | [diff] [blame] | 112 | auto chipPairItr = iv_cache.find(i_chip); |
| 113 | if (iv_cache.end() != chipPairItr) |
Zane Shelley | d0af358 | 2019-09-19 10:48:59 -0500 | [diff] [blame] | 114 | { |
Zane Shelley | fe27b65 | 2019-10-28 11:33:07 -0500 | [diff] [blame] | 115 | auto& hwRegMap = chipPairItr->second; // for ease of use |
Zane Shelley | d0af358 | 2019-09-19 10:48:59 -0500 | [diff] [blame] | 116 | |
| 117 | // Does i_hwReg exist in the cache? |
Zane Shelley | 83da245 | 2019-10-25 15:45:34 -0500 | [diff] [blame] | 118 | auto hwRegPairItr = hwRegMap.find(i_hwReg); |
| 119 | if (hwRegMap.end() != hwRegPairItr) |
Zane Shelley | d0af358 | 2019-09-19 10:48:59 -0500 | [diff] [blame] | 120 | { |
| 121 | return true; |
| 122 | } |
| 123 | } |
| 124 | |
| 125 | return false; |
| 126 | } |
| 127 | |
| 128 | //------------------------------------------------------------------------------ |
| 129 | |
Zane Shelley | fe27b65 | 2019-10-28 11:33:07 -0500 | [diff] [blame] | 130 | BitString& HardwareRegister::Cache::access(const Chip& i_chip, |
Zane Shelley | c477199 | 2019-10-28 22:01:49 -0500 | [diff] [blame] | 131 | const HardwareRegister* i_hwReg) |
Zane Shelley | d0af358 | 2019-09-19 10:48:59 -0500 | [diff] [blame] | 132 | { |
| 133 | // If the entry does not exist, create a new entry. |
Zane Shelley | 83da245 | 2019-10-25 15:45:34 -0500 | [diff] [blame] | 134 | if (!query(i_chip, i_hwReg)) |
Zane Shelley | d0af358 | 2019-09-19 10:48:59 -0500 | [diff] [blame] | 135 | { |
Zane Shelley | c477199 | 2019-10-28 22:01:49 -0500 | [diff] [blame] | 136 | BitString* bs = new BitStringBuffer{i_hwReg->getSize() * 8}; |
Zane Shelley | 7c8faa1 | 2019-10-28 22:26:28 -0500 | [diff] [blame] | 137 | |
Zane Shelley | d0af358 | 2019-09-19 10:48:59 -0500 | [diff] [blame] | 138 | iv_cache[i_chip][i_hwReg] = bs; |
| 139 | } |
| 140 | |
| 141 | // Return a reference to the target entry. |
| 142 | return *(iv_cache[i_chip][i_hwReg]); |
| 143 | } |
| 144 | |
| 145 | //------------------------------------------------------------------------------ |
| 146 | |
| 147 | void HardwareRegister::Cache::flush() |
| 148 | { |
| 149 | // Delete all of the BitStrings. |
Zane Shelley | 5a78fa8 | 2022-09-16 16:49:58 -0500 | [diff] [blame^] | 150 | for (const auto& chipPair : iv_cache) |
Zane Shelley | d0af358 | 2019-09-19 10:48:59 -0500 | [diff] [blame] | 151 | { |
Zane Shelley | 5a78fa8 | 2022-09-16 16:49:58 -0500 | [diff] [blame^] | 152 | for (const auto& hwRegPair : chipPair.second) |
Zane Shelley | d0af358 | 2019-09-19 10:48:59 -0500 | [diff] [blame] | 153 | { |
| 154 | delete hwRegPair.second; |
| 155 | } |
| 156 | } |
| 157 | |
| 158 | // !!! Do not delete the HardwareRegisters !!! |
| 159 | // Those are deleted when the main uninitialize() API is called. |
| 160 | |
| 161 | // Flush the rest of the cache. |
| 162 | iv_cache.clear(); |
| 163 | } |
| 164 | |
| 165 | //------------------------------------------------------------------------------ |
| 166 | |
Zane Shelley | fe27b65 | 2019-10-28 11:33:07 -0500 | [diff] [blame] | 167 | void HardwareRegister::Cache::flush(const Chip& i_chip, |
| 168 | const HardwareRegister* i_hwReg) |
Zane Shelley | d0af358 | 2019-09-19 10:48:59 -0500 | [diff] [blame] | 169 | { |
| 170 | // Does i_chip exist in the cache? |
Zane Shelley | 83da245 | 2019-10-25 15:45:34 -0500 | [diff] [blame] | 171 | auto chipPairItr = iv_cache.find(i_chip); |
| 172 | if (iv_cache.end() != chipPairItr) |
Zane Shelley | d0af358 | 2019-09-19 10:48:59 -0500 | [diff] [blame] | 173 | { |
Zane Shelley | fe27b65 | 2019-10-28 11:33:07 -0500 | [diff] [blame] | 174 | auto& hwRegMap = chipPairItr->second; // for ease of use |
Zane Shelley | d0af358 | 2019-09-19 10:48:59 -0500 | [diff] [blame] | 175 | |
| 176 | // Does i_hwReg exist in the cache? |
Zane Shelley | 83da245 | 2019-10-25 15:45:34 -0500 | [diff] [blame] | 177 | auto hwRegPairItr = hwRegMap.find(i_hwReg); |
| 178 | if (hwRegMap.end() != hwRegPairItr) |
Zane Shelley | d0af358 | 2019-09-19 10:48:59 -0500 | [diff] [blame] | 179 | { |
| 180 | delete hwRegPairItr->second; // delete the BitString |
| 181 | hwRegMap.erase(i_hwReg); // remove the entry for this register |
| 182 | } |
| 183 | |
| 184 | // If i_hwReg was the only entry for i_chip, we can remove i_chip from |
| 185 | // the cache. |
Zane Shelley | 83da245 | 2019-10-25 15:45:34 -0500 | [diff] [blame] | 186 | if (hwRegMap.empty()) |
Zane Shelley | d0af358 | 2019-09-19 10:48:59 -0500 | [diff] [blame] | 187 | { |
| 188 | iv_cache.erase(i_chip); |
| 189 | } |
| 190 | } |
| 191 | } |
| 192 | |
| 193 | //------------------------------------------------------------------------------ |
| 194 | |
Zane Shelley | 871adec | 2019-07-30 11:01:39 -0500 | [diff] [blame] | 195 | } // end namespace libhei |